Towards nanocomputer architecture
CRPIT '02 Proceedings of the seventh Asia-Pacific conference on Computer systems architecture
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Modeling QCA for area minimization in logic synthesis
Proceedings of the 13th ACM Great Lakes symposium on VLSI
A Memory Design in QCAs using the SQUARES Formalism
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Testing of Digital Systems
Defects and Faults in Quantum Cellular Automata at Nano Scale
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
QCADesigner: a rapid design and Simulation tool for quantum-dot cellular automata
IEEE Transactions on Nanotechnology
Testing of quantum cellular automata
IEEE Transactions on Nanotechnology
A method of majority logic reduction for quantum cellular automata
IEEE Transactions on Nanotechnology
Simulation of random cell displacements in QCA
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Bilateral Testing of Nano-scale Fault-Tolerant Circuits
Journal of Electronic Testing: Theory and Applications
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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In this paper, we present a test generation framework for testing of quantum cellular automata (QCA) circuits. QCA is a nanotechnology that has attracted significant recent attention and shows immense promise as a viable future technology. This work is motivated by the fact that the stuck-at fault test set of a circuit is not guaranteed to detect all defects that can occur in its QCA implementation. We show how to generate additional test vectors to supplement the stuck-at fault test set to guarantee that all simulated defects in the QCA gates get detected. Since nanotechnologies will be dominated by interconnects, we also target bridging faults on QCA interconnects. The efficacy of our framework is established through its application to QCA implementations of MCNC benchmarks that use majority gates as primitives.