Defects and Faults in Quantum Cellular Automata at Nano Scale
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Defect Characterization for Scaling of QCA Devices
DFT '04 Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium
Simple 4-Bit Processor Based On Quantum-Dot Cellular Automata (QCA)
ASAP '05 Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors
Test generation for combinational quantum cellular automata (QCA) circuits
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Testing of quantum cellular automata
IEEE Transactions on Nanotechnology
A layout-aware physical design method for constructing feasible QCA circuits
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Modeling and Evaluating Errors Due to Random Clock Shifts in Quantum-Dot Cellular Automata Circuits
Journal of Electronic Testing: Theory and Applications
Binary Adders on Quantum-Dot Cellular Automata
Journal of Signal Processing Systems
An information-theoretic analysis of quantum-dot cellular automata for defect tolerance
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Layout design of manufacturable quantum-dot cellular automata
Microelectronics Journal
Delay-based processing-in-wire for design of QCA serial decimal arithmetic units
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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We analyze the behavior of quantum-dot cellular automata (QCA) building blocks in the presence of random cell displacements. The QCA cells are modeled using the coherence vector description and simulated using QCADesigner. We evaluate various fundamental circuits: the wire, the inverter, the majority gate, and the two-wire crossing approaches: the coplanar crossover and the multilayer crossover. Our results show that different building blocks have different displacement tolerances. The coplanar crossover and inverter perform the weakest. The wire is the most robust. We have found displacement tolerances to be a function of circuit layout and geometry rather than cell size.