Testing of quantum cellular automata

Authors:
M. B. Tahoori;Jing Huang;M. Momenzadeh;F. Lombardi
Affiliations:
Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA;-;-;-
Venue:
IEEE Transactions on Nanotechnology
Year:
2004

Citing 0
Cited 11

Test generation for combinational quantum cellular automata (QCA) circuits

Proceedings of the conference on Design, automation and test in Europe: Proceedings
HDLQ: A HDL environment for QCA design

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Simulation of random cell displacements in QCA

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Analysis of missing and additional cell defects in sequential quantum-dot cellular automata

Integration, the VLSI Journal
A model for computing and energy dissipation of molecular QCA devices and circuits

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Reversible Gates and Testability of One Dimensional Arrays of Molecular QCA

Journal of Electronic Testing: Theory and Applications
Automatic test generation for combinational threshold logic networks

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Detecting Multiple Faults in One-Dimensional Arrays of Reversible QCA Gates

Journal of Electronic Testing: Theory and Applications
Hybrid nanoelectronics: future of computer technology

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A test generation framework for quantum cellular automata circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient design of parity preserving logic in quantum-dot cellular automata targeting enhanced scalability in testing

Microelectronics Journal

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Abstract

There has been considerable research on quantum dot cellular automata (QCA) as a new computing scheme in the nanoscale regimes. The basic logic element of this technology is the majority voter. In this paper, a detailed simulation-based characterization of QCA defects and study of their effects at logic level are presented. Testing of these QCA devices at logic level is investigated and compared with conventional CMOS-based designs. Unique testing features of designs based on this technology are presented and interesting properties have been identified. A testing technique is presented; it requires only a constant number of test vectors to achieve 100% fault coverage with respect to the fault list of the original design. A design-for-test scheme is also presented, which results in the generation of a reduced test set at 100% fault coverage.