Test generation for combinational quantum cellular automata (QCA) circuits
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Journal of Systems Architecture: the EUROMICRO Journal
Reversible Gates and Testability of One Dimensional Arrays of Molecular QCA
Journal of Electronic Testing: Theory and Applications
J-map for quantum dot cellular automata
AEE'08 Proceedings of the 7th WSEAS International Conference on Application of Electrical Engineering
Arithmetic Design on Quantum-Dot Cellular Automata Nanotechnology
SAMOS '08 Proceedings of the 8th international workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
J-map for quantum dot cellular automata
ISCGAV'08 Proceedings of the 8th conference on Signal processing, computational geometry and artificial vision
Hybrid nanoelectronics: future of computer technology
Journal of Computer Science and Technology
A test generation framework for quantum cellular automata circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Binary Adders on Quantum-Dot Cellular Automata
Journal of Signal Processing Systems
A new quantum-dot cellular automata full-adder
Microelectronics Journal
Design of a Goldschmidt iterative divider for quantum-dot cellular automata
NANOARCH '09 Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures
Design of logical structures and characteristics analysis of AOI for quantum dot cellular automata
WSEAS Transactions on Circuits and Systems
Multi-objective optimization of QCA circuits with multiple outputs using genetic programming
Genetic Programming and Evolvable Machines
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The basic Boolean primitive in quantum cellular automata (QCA) is the majority gate. In this paper, a method for reducing the number of majority gates required for computing three-variable Boolean functions is developed to facilitate the conversion of sum-of-products expression into QCA majority logic. Thirteen standard functions are introduced to represent all three-variable Boolean functions and the simplified majority expressions corresponding to these standard functions are presented. We describe a novel method for using these standard functions to convert the sum-of-products expression to majority logic. By applying this method, the hardware requirements for a QCA design can be reduced. As an example, a 1-bit QCA adder is constructed with only three majority gates and two inverters. The adder is designed and simulated using QCADesigner, a design and simulation tool for QCA. We will show that the proposed method is very efficient and fast in deriving the simplified majority expressions in QCA design.