Communications of the ACM
Exploring and exploiting wire-level pipelining in emerging technologies
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Asynchronous Sequential Switching Circuit
Asynchronous Sequential Switching Circuit
Synthesis of Asynchronous State Machines Using A Local Clock
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
ASAP '96 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Gate and throughput optimizations for null convention self-timed digital circuits
Gate and throughput optimizations for null convention self-timed digital circuits
Defects and Faults in Quantum Cellular Automata at Nano Scale
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Design and characterization of an and-or-inverter (AOI) gate for QCA implementation
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Quantum-Dot Cellular Automata (QCA) circuit partitioning: problem modeling and solutions
Proceedings of the 41st annual Design Automation Conference
Incorporating standard CMOS design Process methodologies into the QCA logic design process
IEEE Transactions on Nanotechnology
QCADesigner: a rapid design and Simulation tool for quantum-dot cellular automata
IEEE Transactions on Nanotechnology
Magnetic field and dissipation effects on the charge polarization in quantum cellular automata
IEEE Transactions on Nanotechnology
A method of majority logic reduction for quantum cellular automata
IEEE Transactions on Nanotechnology
Design and characterization of convention self-timed multipliers
IEEE Design & Test
Scalability of Globally Asynchronous QCA (Quantum-Dot Cellular Automata) Adder Design
Journal of Electronic Testing: Theory and Applications
Arithmetic Design on Quantum-Dot Cellular Automata Nanotechnology
SAMOS '08 Proceedings of the 8th international workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
Asynchronous Solutions for Nanomagnetic Logic Circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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The concept of clocking for QCA, referred to as the four-phase clocking, is widely used. However, inherited characteristics of QCA, such as the way to hold state, the way to synchronize data flows, and the way to power QCA cells, make the design of QCA circuits quite different from VLSI and introduce a variety of new design challenges and the most severe challenges are due to the fact that the overall timing of a QCA circuit is mainly dependent upon its layout. This fact is commonly referred to as the ''layout=timing'' problem. To circumvent the problem, a novel self-timed QCA circuit design methodology referred to as the Globally Asynchronous, Locally Synchronous (GALS) Design for QCA is proposed in this paper. The proposed technique can significantly reduce the layout-timing dependency from the global network of QCA devices in a circuit; therefore, considerably flexible QCA circuit design and floorplanning will be possible.