ASAP '96 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Simple 4-Bit Processor Based On Quantum-Dot Cellular Automata (QCA)
ASAP '05 Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors
Efficient and Robust Delay-Insensitive QCA (Quantum-Dot Cellular Automata) Design
DFT '06 Proceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI Systems
HDLQ: A HDL environment for QCA design
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Journal of Systems Architecture: the EUROMICRO Journal
Clocking structures and power analysis for nanomagnet-based logic devices
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Adaptive Latency-Insensitive Protocols
IEEE Design & Test
Design and Test of Digital Circuits by Quantum-Dot Cellular Automata
Design and Test of Digital Circuits by Quantum-Dot Cellular Automata
Turbo NOC: a framework for the design of network-on-chip-based turbo decoder architectures
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Principles of Asynchronous Circuit Design: A Systems Perspective
Principles of Asynchronous Circuit Design: A Systems Perspective
Incorporating standard CMOS design Process methodologies into the QCA logic design process
IEEE Transactions on Nanotechnology
Ultra-Low Power Nanomagnet-Based Computing: A System-Level Perspective
IEEE Transactions on Nanotechnology
An NCL-HDL Snake-Clock-Based Magnetic QCA Architecture
IEEE Transactions on Nanotechnology
A Hardware Viewpoint on Biosequence Analysis: What’s Next?
ACM Journal on Emerging Technologies in Computing Systems (JETC) - Special Issue on Bioinformatics
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In the years to come new solutions will be required to overcome the limitations of scaled CMOS technology. One approach is to adopt Nano-Magnetic Logic Circuits, highly appealing for their extremely reduced power consumption. Despite the interesting nature of this approach, many problems arise when this technology is considered for real designs. The wire is the most critical of these problems from the circuit implementation point of view. It works as a pipelined interconnection, and its delay in terms of clock cycles depends on its length. Serious complications arise at the design phase, both in terms of synthesis and of physical design. One possible solution is the use of a delay insensitive asynchronous logic, Null Convention Logic (NCLTM). Nevertheless its use has many negative consequences in terms of area occupation and speed loss with respect to a Boolean version. In this article we analyze and compare different solutions: nanomagnetic circuits based on full NCL, mixed Boolean-NCL, and fully Boolean logic. We discuss the advantages of these logics, but also the issues they raise. In particular we analyze feedback signals, which, due to their intrinsic pipelined nature, cause errors that still have not found a solution in the literature. The innovative arrangement we propose solves most of the problems and thus soundly increases the knowledge of this technology. The analysis is performed using a VHDL behavioral model we developed and a microprocessor we designed based on this model, as a sound and realistic test bench.