The de Bruijn Multiprocessor Network: A Versatile Parallel Processing and Sorting Network for VLSI
IEEE Transactions on Computers
A Unified Formulation of Honeycomb and Diamond Networks
IEEE Transactions on Parallel and Distributed Systems
A Study on Communication Issues for Systems-on-Chip
Proceedings of the 15th symposium on Integrated circuits and systems design
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
Scalable and Area Efficient Concurrent Interleaver for High Throughput Turbo-Decoders
DSD '04 Proceedings of the Digital System Design, EUROMICRO Systems
Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Application specific NoC design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
ASIP-based multiprocessor SoC design for simple and double binary turbo decoding
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding
Proceedings of the conference on Design, automation and test in Europe
Design to Minimize Diameter on Building-Block Network
IEEE Transactions on Computers
A Design for Directed Graphs with Minimum Diameter
IEEE Transactions on Computers
de Bruijn graph as a low latency scalable architecture for energy efficient massive NoCs
Proceedings of the conference on Design, automation and test in Europe
A reconfigurable ASIP for convolutional and turbo decoding in an SDR environment
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Digraphs: Theory, Algorithms and Applications
Digraphs: Theory, Algorithms and Applications
Reliable network-on-chip based on generalized de Bruijn graph
HLDVT '07 Proceedings of the 2007 IEEE International High Level Design Validation and Test Workshop
Bit-level extrinsic information exchange method for double-binary turbo codes
IEEE Transactions on Circuits and Systems II: Express Briefs
Low-power memory-reduced traceback MAP decoding for double-binary convolutional turbo decoder
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special issue on ISCAS2008
Flexible Architectures for LDPC Decoders Based on Network on Chip Paradigm
DSD '09 Proceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools
From parallelism levels to a multi-ASIP architecture for turbo decoding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Layout-Aware Analysis of Networks-on-Chip and Traditional Interconnects for MPSoCs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On chip interconnects for multiprocessor turbo decoding architectures
Microprocessors & Microsystems
Asynchronous Solutions for Nanomagnetic Logic Circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Flexible LDPC decoder architectures
VLSI Design - Special issue on Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation
A network-on-chip-based turbo/LDPC decoder architecture
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
A Hardware Viewpoint on Biosequence Analysis: What’s Next?
ACM Journal on Emerging Technologies in Computing Systems (JETC) - Special Issue on Bioinformatics
Nanoarray architectures multilevel simulation
ACM Journal on Emerging Technologies in Computing Systems (JETC) - Special Issue on Reliability and Device Degradation in Emerging Technologies and Special Issue on WoSAR 2011
| Hi-index | 0.00 |
This paper proposes a general framework for the design and simulation of network-on-chip-based turbo decoder architectures. Several parameters in the design space are investigated, namely, network topology, parallelism degree, the rate at which messages are sent by processing nodes over the network, and routing strategy. The main results of this analysis are as follows: 1) the most suited topologies to achieve high throughput with a limited complexity overhead are generalized de Bruijn and generalized Kautz topologies and 2) depending on the throughput requirements, different parallelism degrees, message injection rates, and routing algorithms can be used to minimize the network area overhead.