SIMD processor-based turbo decoder supporting multiple third-generation wireless standards
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Area-efficient high-throughput MAP decoder architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power memory-reduced traceback MAP decoding for double-binary convolutional turbo decoder
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special issue on ISCAS2008
Turbo NOC: a framework for the design of network-on-chip-based turbo decoder architectures
IEEE Transactions on Circuits and Systems Part I: Regular Papers
A network-on-chip-based turbo/LDPC decoder architecture
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Reconfigurable Parallel Turbo Decoder Design for Multiple High-Mobility 4G Systems
Journal of Signal Processing Systems
| Hi-index | 0.00 |
Nonbinary turbo codes have many advantages over single-binary turbo codes, but their decoder implementations require much more memory, particularly for storing symbolic extrinsic information to be exchanged between two soft-input-soft-output (SISO) decoders. To reduce the memory size required for double-binary turbo decoding, this paper presents a new method to convert symbolic extrinsic information to bit-level information and vice versa. By exchanging bit-level extrinsic information, the number of extrinsic information values to be exchanged in double-binary turbo decoding is reduced to the same amount as that in single-binary turbo decoding. A double-binary turbo decoder is designed for the WiMAX standard to verify the proposed method, which reduces tbe total memory size by 20%.