VLSI architectures for turbo codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DSP implementation issues for UMTS-channel coding
ICASSP '00 Proceedings of the Acoustics, Speech, and Signal Processing, 2000. on IEEE International Conference - Volume 06
Design of fixed-point iterative decoders for concatenated codes with interleavers
IEEE Journal on Selected Areas in Communications
Bit-level extrinsic information exchange method for double-binary turbo codes
IEEE Transactions on Circuits and Systems II: Express Briefs
System architecture for 3GPP LTE modem using a programmable baseband processor
SOC'09 Proceedings of the 11th international conference on System-on-chip
Implementation of a High Throughput 3GPP Turbo Decoder on GPU
Journal of Signal Processing Systems
Implementation of a Radix-4, Parallel Turbo Decoder and Enabling the Multi-Standard Support
Journal of Signal Processing Systems
System Architecture for 3GPP-LTE Modem using a Programmable Baseband Processor
International Journal of Embedded and Real-Time Communication Systems
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A programmable turbo decoder is designed to support multiple third-generation wireless communication standards. We propose a hybrid architecture of hardware and software, which has small size, low power, and high performance like hardware implementations, as well as the flexibility and programmability of software. It mainly consists of a configurable hardware soft-input-soft-output (SISO) decoder and a 16-b single-instruction multiple-data processor, which is equipped with five processing elements and special instructions customized for interleaving in order to provide interleaved data at the speed of the hardware SISO. A fast and flexible software implementation of the block interleaving algorithm is also proposed. The interleaver generation is split into two parts, preprocessing and on-the-fly generation, to reduce the timing overhead of changing the interleaver structure. We present detailed descriptions of the interleaving implementation applied to the W-CDMA and cdma2000 standard turbo codes. The decoder occupies 8.90 mm2 in a 0.25-µm CMOS with five metal layers and exhibits the maximum decoding rate of 5.48 Mb/s.