Energy Efficient VLSI Architecture for Linear Turbo Equalizer
Journal of VLSI Signal Processing Systems
High Speed Max-Log-MAP Turbo SISO Decoder Implementation Using Branch Metric Normalization
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Beyond 3G wireless communication system prototype
Proceedings of the 17th ACM Great Lakes symposium on VLSI
SIMD processor-based turbo decoder supporting multiple third-generation wireless standards
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Decoding of high rate convolutional codes using the dual trellis
IEEE Transactions on Information Theory
Stochastic decoding of turbo codes
IEEE Transactions on Signal Processing
Fixed-point MAP decoding of channel codes
EURASIP Journal on Advances in Signal Processing - Special issue on quantization of VLSI digital signal processing systems
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We discuss the effects of quantization on the performance of the iterative decoding algorithm of concatenated codes with interleavers. Quantization refers here to the log-likelihood ratios coming from the soft demodulator and to the extrinsic information passed from one stage of the decoder to the next. We discuss the cases of a single soft-input soft-output (SISO) module, in its additive log-likelihood version (L-SISO), performing sequentially all iterations (an implementation solution coping with medium-low data rate as compared with the hardware clock), and that of a pipelined structure in which a dedicated hardware is in charge of each SISO operation (an implementation suitable for high data rates). We give design rules in both cases, and show that a suitable rescaling of the extrinsic information yields almost ideal performance with the same number of bits (five) representing both log-likelihood ratios and extrinsic information at any decoder stage