Probability, random processes, and estimation theory for engineers
Probability, random processes, and estimation theory for engineers
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Memory optimization of MAP turbo decoder algorithms
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy efficient turbo decoding for 3G mobile
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
VLSI architectures for SISO-APP decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Minimum mean squared error equalization using a priori information
IEEE Transactions on Signal Processing
IEEE Journal on Selected Areas in Communications
Design of fixed-point iterative decoders for concatenated codes with interleavers
IEEE Journal on Selected Areas in Communications
Turbo equalization: adaptive equalization and channel decoding jointly optimized
IEEE Journal on Selected Areas in Communications
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In this paper, energy efficient VLSI architectures for linear turbo equalization are studied. Linear turbo equalizers exhibit dramatic bit error rate (BER) improvement over conventional equalizers by enabling a form of joint equalization and decoding in which soft information is iteratively exchanged between the equalizer and decoder. However, turbo equalizers can be computationally complex and hence require significant power consumption. In this paper, we present an energy-efficient VLSI architecture for such linear turbo equalizers. Key architectural techniques include elimination of redundant operations and early termination. Early termination enables powering down parts of the soft-input soft-output (SISO) equalizer and decoder thereby saving power. Simulation results show that energy savings in the range 30–60% and 10–60% are achieved in equalization and decoding, respectively. Furthermore, we present finite precision requirements of the linear turbo equalizer and an efficient rescaling method to prevent overflow.