A 50 Mbit/s iterative turbo-decoder
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Power-efficient layered turbo decoder processor
Proceedings of the conference on Design, automation and test in Europe
Energy efficient turbo decoding for 3G mobile
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Architectural strategies for low-power VLSI turbo decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Memory Power Reduction for High-Speed Implementation of Turbo Codes
Journal of VLSI Signal Processing Systems
Implementation of Near Shannon Limit Error-Correcting Codes Using Reconfigurable Hardware
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
A Flexible and Energy-Efficient Coarse-Grained Reconfigurable Architecture for Mobile Systems
The Journal of Supercomputing
VLSI architectures for SISO-APP decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power design of turbo decoder with exploration of energy-throughput trade-off
Compilers and operating systems for low power
Interleaving on Parallel DSP Architectures
Journal of VLSI Signal Processing Systems
Design and implementation of low-energy turbo decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
VLSI Architectural design tradeoffs for sliding-window Log-MAP decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Memory sub-banking scheme for high throughput MAP-based SISO decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of VLSI Signal Processing Systems
Beyond 3G wireless communication system prototype
Proceedings of the 17th ACM Great Lakes symposium on VLSI
SIMD processor-based turbo decoder supporting multiple third-generation wireless standards
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamically configurable bus topologies for high-performance on-chip communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power memory-reduced traceback MAP decoding for double-binary convolutional turbo decoder
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special issue on ISCAS2008
Partial iterative decoding for binary turbo codes via cross-entropy based bit selection
IEEE Transactions on Communications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
From parallelism levels to a multi-ASIP architecture for turbo decoding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Flexible LDPC/Turbo Decoder Architecture
Journal of Signal Processing Systems
VLSI architectures for sliding-window-based space-time turbo trellis code decoders
Journal of Electrical and Computer Engineering - Special issue on Implementations of Signal-Processing Algorithms for OFDM Systems
Reconfigurable Parallel Turbo Decoder Design for Multiple High-Mobility 4G Systems
Journal of Signal Processing Systems
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A great interest has been gained in recent years by a new error-correcting code technique, known as "turbo coding", which has been proven to offer performance closer to the Shannon's limit than traditional concatenated codes. In this paper, several very large scale integration (VLSI) architectures suitable for turbo decoder implementation are proposed and compared in terms of complexity and performance; the impact on the VLSI complexity of system parameters like the state number, number of iterations, and code rate are evaluated for the different solutions. The results of this architectural study have then been exploited for the design of a specific decoder, implementing a serial concatenation scheme with 2/3 and 3/4 codes; the designed circuit occupies 35 mm/sup 2/, supports a 2 Mb/s data rate, and for a bit error probability of 10/sup -6/, yields a coding gain larger than 7 dB, with ten iterations.