Reconfigurable Parallel Turbo Decoder Design for Multiple High-Mobility 4G Systems

Authors:
Cheng-Hung Lin;Chun-Yu Chen;En-Jui Chang;An-Yeu Wu
Affiliations:
Department of Electrical Engineering, Yuan Ze University, Jungli, Republic of China 32003;Silicon Motion Technology Corp., Sindian, Republic of China 23141;Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, Taipei, Republic of China 10617;Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, Taipei, Republic of China 10617
Venue:
Journal of Signal Processing Systems
Year:
2013

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Abstract

For high-mobility 4G applications of LTE-A and WiMAX-2 systems, this paper presents a dual-standard turbo decoder design with the following three techniques. 1) Circular parallel decoding reduces decoding latency and improves throughput rate. 2) Collision-free vectorizable dual-standard parallel interleaver enhances hardware utilization of the interleaving address generator. 3) One-bank extrinsic buffer design with bit-level extrinsic information exchange reduces size of the extrinsic buffer compared with the two-bank extrinsic buffer design. Furthermore, a multi-standard turbo decoder chip is fabricated in a core area of 3.38 mm2 by 90 nm CMOS process. This chip is maximally measured at 152 MHz with 186.1 Mbps for LTE-A standard and 179.3 Mbps for WiMAX-2 standard.