Design and implementation of low-energy turbo decoders

Authors:
Jagadeesh Kaza;Chaitali Chakrabarti
Affiliations:
Texas Instruments Incorporated, Dallas, TX;Department of Electrical Engineering, Arizona State University, Tempe, AZ
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2004

Citing 10
Cited 5

VLSI architectures for turbo codes

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wattch: a framework for architectural-level power analysis and optimizations

Proceedings of the 27th annual international symposium on Computer architecture
Design and Implementation of a Low Complexity VLSITurbo-Code Decoder Architecture for LowEnergy Mobile Wireless Communications

Journal of VLSI Signal Processing Systems - Special issue on recent advances in the design and implementation of signal processing systems
Reducing power consumption of turbo-code decoder using adaptive iteration with variable supply voltage

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Memory optimization of MAP turbo decoder algorithms

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy efficient turbo decoding for 3G mobile

ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Architectural strategies for low-power VLSI turbo decoders

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Area-efficient high-speed decoding schemes for turbo decoders

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Iterative decoding of binary block and convolutional codes

IEEE Transactions on Information Theory
Design and analysis of turbo codes on Rayleigh fading channels

IEEE Journal on Selected Areas in Communications

Multiple-input turbo code for secure data aggregation and source-channel coding in wireless sensor networks

International Journal of Sensor Networks
Traceback-Based Optimizations for Maximum a Posteriori Decoding Algorithms

Journal of Signal Processing Systems
Relaxation dynamics in stochastic iterative decoders

IEEE Transactions on Signal Processing
Area-efficient scalable map processor design for high-throughput multistandard convolutional turbo decoding

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reconfigurable Parallel Turbo Decoder Design for Multiple High-Mobility 4G Systems

Journal of Signal Processing Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

Turbo codes have been chosen in the third generation cellular standard for high-throughput data communication. These codes achieve remarkably low bit error rates at the expense of high-computational complexity. Thus for hand held communication devices, designing energy efficient Turbo decoders is of great importance. In this paper, we present a suite of MAP-based Turbo decoding algorithms with energy-quality tradeoffs for additive white Gaussian noise (AWGN) and fading channels. We derive these algorithms by applying approximation techniques such as pruning the trellis, reducing the number of states, scaling the extrinsic information, applying sliding window, and early termination on the MAP-based algorithm. We show that a combination of these techniques can result in energy savings of 53.2% (50.0%) on a general purpose processor and energy savings of 80.66% (80.81%) on a hardware implementation for AWGN (fading) channels if a drop of 0.35 dB in SNR can be tolerated, at a bit error rate (BER) of 10-5. We also propose an adaptive Turbo decoding technique that is suitable for low power operation in noisy environments.