VLSI architectures for turbo codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Memory optimization of MAP turbo decoder algorithms
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
VLSI architectures for SISO-APP decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-Power Hybrid Turbo Decoding Based on Reverse Calculation
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Bit-level extrinsic information exchange method for double-binary turbo codes
IEEE Transactions on Circuits and Systems II: Express Briefs
Area-efficient high-speed decoding schemes for turbo decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Journal on Selected Areas in Communications
Reconfigurable turbo decoder with parallel architecture for 3GPP LTE system
IEEE Transactions on Circuits and Systems II: Express Briefs
Turbo NOC: a framework for the design of network-on-chip-based turbo decoder architectures
IEEE Transactions on Circuits and Systems Part I: Regular Papers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reconfigurable Parallel Turbo Decoder Design for Multiple High-Mobility 4G Systems
Journal of Signal Processing Systems
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Iterative decoding of convolutional turbo code (CTC) has a large memory power consumption. To reduce the power consumption of the state metrics cache (SMC), low-power memory-reduced traceback maximum a posteriori algorithm (MAP) decoding is proposed. Instead of storing all state metrics, the traceback MAP decoding reduces the size of the SMC by accessing difference metrics. The proposed traceback computation requires no complicated reversion checker, path selection, and reversion flag cache. For double-binary (DB) MAP decoding, radix-2 × 2 and radix-4 traceback structures are introduced to provide a tradeoff between power consumption and operating frequency. These two traceback structures achieve an around 20% power reduction of the SMC, and around 7% power reduction of the DB MAP decoders. In addition, a high-throughput 12-mode WiMAX CTC decoder applying the proposed radix-2 × 2 traceback structure is implemented by using a 0.13-µm CMOS process in a core area of 7.16 mm2. Based on postlayout simulation results, the proposed decoder achieves a maximum throughput rate of 115.4 Mbps and an energy efficiency of 0.43 nJ/bit per iteration.