Design of a transport triggered vector processor for turbo decoding

Authors:
Shahriar Shahabuddin;Janne Janhunen;Markku Juntti;Amanullah Ghazi;Olli Silvén
Affiliations:
Department of Communications Engineering and Centre for Wireless Communications, University of Oulu, Oulu, Finland;Department of Communications Engineering and Centre for Wireless Communications, University of Oulu, Oulu, Finland;Department of Communications Engineering and Centre for Wireless Communications, University of Oulu, Oulu, Finland;Department of Computer Science and Engineering, University of Oulu, Oulu, Finland;Department of Computer Science and Engineering, University of Oulu, Oulu, Finland
Venue:
Analog Integrated Circuits and Signal Processing
Year:
2014

Citing 7
Cited 0

Microprocessor Architectures: From VLIW to Tta

Microprocessor Architectures: From VLIW to Tta
Hardware/Software Trade-Offs for Advanced 3G Channel Coding

Proceedings of the conference on Design, automation and test in Europe
New Schemes in Clustered VLIW Processors Applied to Turbo Decoding

ASAP '06 Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors
High-speed recursion architectures for MAP-based turbo decoders

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Customized Exposed Datapath Soft-Core Design Flow with Compiler Support

FPL '10 Proceedings of the 2010 International Conference on Field Programmable Logic and Applications
A low-complexity turbo decoder architecture for energy-efficient wireless sensor networks

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reconfigurable Parallel Turbo Decoder Design for Multiple High-Mobility 4G Systems

Journal of Signal Processing Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

In order to meet the requirement of high data rates for next generation wireless systems, efficient implementations of receiver algorithms are essential. On the other hand, faster time-to-market motivates the investigation of programmable implementations. This paper presents a novel design of a programmable turbo decoder as an application-specific instruction-set processor (ASIP) using transport triggered architecture (TTA). The processor architecture is designed in such a manner that it can be programmed with high level language to support different suboptimal maximum a posteriori (MAP) algorithms in a single TTA processor. The design enables the designer to change the algorithms according to the frame error rate performance requirement. A quadratic polynomial permutation interleaver is used for contention-free memory access and to make the processor 3GPP LTE compliant. Several optimization techniques to enable real time processing on programmable platforms are introduced. The essential parts of the turbo decoding algorithm are designed with vector function units. Unlike most other turbo decoder ASIPs, high level language is used to program the processor to meet the time-to-market requirements. With a single iteration, 68.35 Mbps decoding speed is achieved for the max-log-MAP algorithm at a clock frequency of 210 MHz on 90 nm technology.