Proceedings of the conference on Design, automation and test in Europe
Joint Source-Channel Decoding ASIP Architecture for Sensor Networks
ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
A reconfigurable ASIP for convolutional and turbo decoding in an SDR environment
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design space exploration of the turbo decoding algorithm on GPUs
CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems
Design of a transport triggered vector processor for turbo decoding
Analog Integrated Circuits and Signal Processing
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State-of-the-art communication standards make extensive use of Turbo codes. The complex and power consuming designs that currently implement the turbo decoder expose the need for innovative solutions. In recent years the area of application specific processors has attracted the attention of the research community and important advances have been made possible. This work introduces an ASIP architecture for SISO Turbo decoding based on a dual-clustered VLIW processor. The machine deals with instructions of up to 21 operands in an innovative way, the fetching and asserting of data is serialized and the addressing is automatized and transparent for the programmer. An optimized architecture is achieved, flexible enough to comply with leading edge standards and adaptable to demanding hardware constraints.