Digital Communication Receivers: Synchronization, Channel Estimation, and Signal Processing
Digital Communication Receivers: Synchronization, Channel Estimation, and Signal Processing
Principles of Digital Communication and Coding
Principles of Digital Communication and Coding
Hardware/Software Trade-Offs for Advanced 3G Channel Coding
Proceedings of the conference on Design, automation and test in Europe
Channel Decoder Architecture for 3G Mobile Wireless Terminals
Proceedings of the conference on Design, automation and test in Europe - Volume 3
A multi-standard channel-decoder for base-station applications
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Communication Centric Architectures for Turbo-Decoding on Embedded Multiprocessors
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Design and Analysis of a Programmable Single-Chip Architecture for DVB-T Base-Band Receiver
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Scalable System Architecture for High-Throughput Turbo-Decoders
Journal of VLSI Signal Processing Systems
ASIP-based multiprocessor SoC design for simple and double binary turbo decoding
Proceedings of the conference on Design, automation and test in Europe: Proceedings
SODA: A Low-power Architecture For Software Radio
Proceedings of the 33rd annual international symposium on Computer Architecture
New Schemes in Clustered VLIW Processors Applied to Turbo Decoding
ASAP '06 Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors
Scalable reconfigurable channel decoder architecture for future wireless handsets
Proceedings of the conference on Design, automation and test in Europe
Turbo NOC: a framework for the design of network-on-chip-based turbo decoder architectures
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Reconfigurable Architecture for Deinterlacer based on Algorithm/Architecture Co-Design
Journal of Signal Processing Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A case study on error resilient architectures for wireless communication
ARCS'12 Proceedings of the 25th international conference on Architecture of Computing Systems
International Journal of Reconfigurable Computing - Special issue on Selected Papers from the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2011)
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Future mobile and wireless communication networks require flexible modem architectures to support seamless services between different network standards. Hence, a common hardware platform that can support multiple protocols implemented or controlled by software, generally referred to as software defined radio (SDR), is essential. This paper presents a family of dynamically reconfigurable application-specific instruction-set processors (ASIPs) for channel coding in wireless communication systems. As a weakly programmable intellectual property (IP) core, it can implement trellis-based channel decoding in a SDR environment. It features binary convolutional decoding, and turbo decoding for binary as well as duobinary turbo codes for all current and upcoming standards. The ASIP consists of a specialized pipeline with 15 stages and a dedicated communication and memory infrastructure. Logic synthesis revealed a maximum clock frequency of 400 MHz and an area of 0.11 mm2 for the processor's logic using a low power 65-nm technology. Memories require another 0.31 mm2. Simulation results for Viterbi and turbo decoding demonstrate maximum throughput of 196 and 34 Mb/s, respectively. The ASIP hence outperforms state-of-the-art decoder architectures targeting software defined radio by at least a factor of three while consuming only 60 % or less of the logic area.