IEEE Transactions on Computers
Efficient VLSI Architectures for Multiuser Channel Estimation in Wireless Base-Station Receivers
Journal of VLSI Signal Processing Systems
High-Level State Machine Specification and Synthesis
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
RaPiD - Reconfigurable Pipelined Datapath
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
Describing instruction set processors using nML
EDTC '95 Proceedings of the 1995 European conference on Design and Test
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Architecture Exploration for a Reconfigurable Architecture Template
IEEE Design & Test
SODA: A Low-power Architecture For Software Radio
Proceedings of the 33rd annual international symposium on Computer Architecture
Vector processing as an enabler for software-defined radio in handheld devices
EURASIP Journal on Applied Signal Processing
The sandbridge SB3011 platform
EURASIP Journal on Embedded Systems
Towards software defined radios using coarse-grained reconfigurable hardware
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A design flow for architecture exploration and implementation of partially reconfigurable processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A reconfigurable ASIP for convolutional and turbo decoding in an SDR environment
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Iris: an architecture for cognitive radio networking testbeds
IEEE Communications Magazine
A scalable VLSI architecture for soft-input soft-output depth-first sphere decoding
IEEE Transactions on Circuits and Systems II: Express Briefs
IEEE Transactions on Wireless Communications
Performance comparisons of channel estimation techniques in multipath fading CDMA
IEEE Transactions on Wireless Communications
FLEXDET: Flexible, Efficient Multi-Mode MIMO Detection Using Reconfigurable ASIP
FCCM '12 Proceedings of the 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines
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Due to the fast changing wireless communication standards coupled with strict performance constraints, the demand for flexible yet high-performance architectures is increasing. To tackle the flexibility requirement, software-defined radio (SDR) is emerging as an obvious solution, where the underlying hardware implementation is tuned via software layers to the varied standards depending on power-performance and quality requirements leading to adaptable, cognitive radio. In this paper, we conduct a case study for representatives of two complexity classes of WCDMA channel estimation algorithms and explore the effect of flexibility on energy efficiency using different implementation options. Furthermore, we propose new design guidelines for both highly specialized architectures and highly flexible architectures using high-level synthesis, to enable the required performance and flexibility to support multiple applications. Our experiments with various design points show that the resulting architectures meet the performance constraints of WCDMA and a wide range of options are offered for tuning such architectures depending on power/performance/area constraints of SDR.