The sandbridge SB3011 platform

Authors:
John Glossner;Daniel Iancu;Mayan Moudgill;Gary Nacer;Sanjay Jinturkar;Stuart Stanley;Michael Schulte
Affiliations:
Sandbridge Technologies, Inc., White Plains, NY;Sandbridge Technologies, Inc., White Plains, NY;Sandbridge Technologies, Inc., White Plains, NY;Sandbridge Technologies, Inc., White Plains, NY;Sandbridge Technologies, Inc., White Plains, NY;Sandbridge Technologies, Inc., White Plains, NY;Sandbridge Technologies, Inc., White Plains, NY
Venue:
EURASIP Journal on Embedded Systems
Year:
2007

Citing 19
Cited 6

The architecture of HEP

on Parallel MIMD computation: HEP supercomputer and its applications
Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint

ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Simultaneous multithreading: maximizing on-chip parallelism

ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Pthreads programming

Pthreads programming
LISA—machine description language for cycle-accurate models of programmable DSP architectures

Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A universal technique for fast and flexible instruction-set architecture simulation

Proceedings of the 39th annual Design Automation Conference
Computer Architecture: Concepts and Evolution

Computer Architecture: Concepts and Evolution
An ultra-fast instruction set simulator

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power: A First-Class Architectural Design Constraint

Computer
A survey of processors with explicit multithreading

ACM Computing Surveys (CSUR)
A Framework for Simulating Heterogeneous Virtual Processors

SS '99 Proceedings of the Thirty-Second Annual Simulation Symposium
GSM Enhanced Full Rate Speech Codec

ICASSP '97 Proceedings of the 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '97)-Volume 2 - Volume 2
Design Alternatives for Parallel Saturating Multioperand Adders

ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
A case study of mapping a software-defined radio (SDR) application on a reconfigurable DSP core

Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Detecting overflow detection

Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
SODA: A Low-power Architecture For Software Radio

Proceedings of the 33rd annual international symposium on Computer Architecture
The Problem with Threads

Computer
Vector processing as an enabler for software-defined radio in handheld devices

EURASIP Journal on Applied Signal Processing
Observations on power-efficiency trends in mobile communication devices

SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation

CORDIC instruction set extensions for matrix decompositions on software defined radio processors

Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
Heterogeneous vs homogeneous MPSoC approaches for a mobile LTE modem

Proceedings of the Conference on Design, Automation and Test in Europe
CORDIC instructions for LDPC decoding on SDR platforms

Analog Integrated Circuits and Signal Processing
Instruction Set Extensions for Matrix Decompositions on Software Defined Radio Architectures

Journal of Signal Processing Systems
High-level design space and flexibility exploration for adaptive, energy-efficient WCDMA channel estimation architectures

International Journal of Reconfigurable Computing - Special issue on Selected Papers from the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2011)
Tomahawk: Parallelism and heterogeneity in communications signal processing MPSoCs

ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper describes the Sandbridge Sandblaster real-time software-defined radio platform. Specifically, we describe the SB3011 system-on-a-chip multiprocessor. We describe the software development system that enables real-time execution of communications and multimedia applications. We provide results for a number of interesting communications and multimedia systems including UMTS, DVB-H, WiMAX, WiFi, and NTSC video decoding. Each processor core achieves 600MHz at 0.9V operation while typically dissipating 75mW in 90nm technology. The entire chip typically dissipates less than 500mW at 0.9V.