The sandbridge SB3011 platform
EURASIP Journal on Embedded Systems
Multi-core DSP for base stations: large and small
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Design and Implementation of a GALS Adapter for ANoC Based Architectures
ASYNC '09 Proceedings of the 2009 15th IEEE Symposium on Asynchronous Circuits and Systems (async 2009)
A Communication and configuration controller for NoC based reconfigurable data flow architecture
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
An Open and Reconfigurable Platform for 4G Telecommunication: Concepts and Application
DSD '09 Proceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools
Proceedings of the Conference on Design, Automation and Test in Europe
Multiprocessor System-on-Chip (MPSoC) Technology
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Partitioning and mapping on NoC-Based MPSoC: an energy consumption saving approach
Proceedings of the 4th International Workshop on Network on Chip Architectures
Journal of Electrical and Computer Engineering - Special issue on ESL Design Methodology
Exploring alternative flexible OpenCL (FlexCL) core designs in FPGA-based MPSoC systems
Proceedings of the 2013 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools
Power-aware dynamic mapping heuristics for NoC-based MPSoCs using a unified model-based approach
ACM Transactions on Embedded Computing Systems (TECS)
Exploring parallelization for medium access schemes on many-core software defined radio architecture
Proceedings of the second workshop on Software radio implementation forum
Providing multiple hard latency and throughput guarantees for packet switching networks on chip
Computers and Electrical Engineering
MPSoC based on Transport Triggered Architecture for baseband processing of an LTE receiver
Journal of Systems Architecture: the EUROMICRO Journal
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Applications like 4G baseband modem require single-chip implementation to meet the integration and power consumption requirements. These applications demand a high computing performance with real-time constraints, low-power consumption and low cost. With the rapid evolution of telecom standards and the increasing demand for multi-standard products, the need for flexible baseband solutions is growing. The concept of Multi-Processor System-on-Chip (MPSoC) is well adapted to enable hardware reuse between products and between multiple wireless standards in the same device. Heterogeneous architectures are well known solutions but they have limited flexibility. Based on the experience of two heterogeneous Software Defined Radio (SDR) telecom chipsets, this paper presents the homoGENEous Processor arraY (GENEPY) platform for 4G applications. This platform is built with Smart ModEm Processors (SMEP) interconnected with a Network-on-Chip. The SMEP, implemented in 65nm low-power CMOS, can perform 3.2 GMAC/s with 77 GBits/s internal bandwidth at 400MHz. Two implementations of homogeneous GENEPY are compared to a heterogeneous platform in terms of silicon area, performance and power consumption. Results show that a homogeneous approach can be more efficient and flexible than a heterogeneous approach in the context of 4G Mobile Terminals.