MOVE: a framework for high-performance processor design
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
TTAs: missing the ILP complexity wall
Journal of Systems Architecture: the EUROMICRO Journal - Special double issue on microprocessor architecture
OFDM Baseband Receiver Design for Wireless Communications
OFDM Baseband Receiver Design for Wireless Communications
System architecture for 3GPP LTE modem using a programmable baseband processor
SOC'09 Proceedings of the 11th international conference on System-on-chip
On the performance of 3GPP LTE baseband using SB3500
SOC'09 Proceedings of the 11th international conference on System-on-chip
Heterogeneous vs homogeneous MPSoC approaches for a mobile LTE modem
Proceedings of the Conference on Design, Automation and Test in Europe
Low-Power Application-Specific Processor for FFT Computations
Journal of Signal Processing Systems
ML estimation of time and frequency offset in OFDM systems
IEEE Transactions on Signal Processing
IEEE Transactions on Consumer Electronics
Multicarrier modulation for data transmission: an idea whose time has come
IEEE Communications Magazine
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Wireless communication over LTE (long term evolution) brings several design challenges to industry and academia, due to its high throughput demand. Specially in the case of hand held mobile devices where the power budget is very limited and high throughput requires more computation power. On the other hand, the industry is struggling for flexible hardware solution, a Software Defined Radio (SDR), to amortize huge costs of hardware changes to suit the continued evolution in wireless standards. In this article, an MPSoC design has been presented for the baseband processing of a 20MHz LTE system. Transport Triggered Architecture (TTA) has been preferred over conventional DSPs/VLIW architectures as processing element (PE) of MPSoC. Processing tasks are statically scheduled. Synchronization among the PEs is based on polling of a shared memory space. In addition an approach is presented to organize I/O buffer in such a way that the stalling probability of a PE should be reduced to exploit efficiently data and task level parallelism. The total power consumption by all the PEs synthesized on 130nm technology at 200MHz and 1.5V is 105.04mW. The total energy consumption to process one subframe including carrier recovery is 0.0767mJ. Our study shows that TTA architecture brings several improvements in conventional SIMD/VLIW architectures. TTA as contrary to other run time designs has a guaranteed performance and lower energy consumption due to the fact that all the data dependency/independency issues are resolved at compile time. Further, it is also true due to the fact that TTA has a reduced register file (RF) traffic, number of RF ports and lower overall cycle count for a given task. To the best of author's knowledge this article is among the first few published articles on LTE receiver implementation with published figures like time, frequency, power and perhaps the first article explaining further in detail about data access pattern to process an LTE subframe, memory organization, subsystem interconnection, and synchronization.