IEEE Transactions on Circuits and Systems II: Express Briefs
A fully-asynchronous low-power framework for GALS NoC integration
Proceedings of the Conference on Design, Automation and Test in Europe
Heterogeneous vs homogeneous MPSoC approaches for a mobile LTE modem
Proceedings of the Conference on Design, Automation and Test in Europe
Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs
Proceedings of the Conference on Design, Automation and Test in Europe
A low latency wormhole router for asynchronous on-chip networks
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Asynchronous spatial division multiplexing router
Microprocessors & Microsystems
Quasi delay-insensitive high speed two-phase protocol asynchronous wrapper for network on chips
Journal of Computer Science and Technology
Proceedings of the Conference on Design, Automation and Test in Europe
Exploring pausible clocking based GALS design for 40-nm system integration
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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To the casual observer, glitches occurring in quasi delay-insensitive logic would appear to cause incorrect operation and render the circuits unusable. This paper presents an informal analysis of the effects of glitches occurring on the long interconnect ...