CMOS design of the tree arbiter element
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Lowering power consumption in clock by using globally asynchronous locally synchronous design style
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
Delay-Insensitive, Point-to-Point Interconnect Using M-of-N Codes
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
MOUSETRAP: Ultra-High-Speed Transition-Signaling Asynchronous Pipelines
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link
ASYNC '07 Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems
Delay/Phase Regeneration Circuits
ASYNC '07 Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems
Design and DfT of a high-speed area-efficient embedded asynchronous FIFO
Proceedings of the conference on Design, automation and test in Europe
Integration, the VLSI Journal
A GALS Infrastructure for a Massively Parallel Multiprocessor
IEEE Design & Test
The design of high-performance dynamic asynchronous pipelines: lookahead style
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computers
Integration, the VLSI Journal
Design and Implementation of a GALS Adapter for ANoC Based Architectures
ASYNC '09 Proceedings of the 2009 15th IEEE Symposium on Asynchronous Circuits and Systems (async 2009)
Robust differential asynchronous nanoelectronic circuits
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Synchronization and Arbitration in Digital Systems
Synchronization and Arbitration in Digital Systems
Asynchronous spatial division multiplexing router
Microprocessors & Microsystems
Area efficient asynchronous SDM routers using 2-stage clos switches
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Asynchronous on-chip networks are power efficient and tolerant to process variation but they are slower than synchronous on-chip networks. A low latency asynchronous wormhole router is proposed using sliced sub-channels and the look-ahead pipeline. Channel slicing removes the C-element tree in the completion detection circuit and converts a channel into multiple independent sub-channels reducing the cycle period. The look-ahead pipeline uses the early evaluation protocol to reduce cycle period. Using the lookahead pipeline on the pipeline stages with the maximal cycle period improves the overall throughput. The router is a pure standard cell design implemented by a 0.13 μm technology. The cycle period of the router at the typical corner is 1.7 ns, providing 2.35GByte/sec throughput per port.