Communications of the ACM
Self-timed rings and their application to division
Self-timed rings and their application to division
Investigation into micropipeline latch design styles
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Static timing analysis for self resetting circuits
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Lazy transition systems: application to timing optimization of asynchronous circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
IEEE Spectrum
Clock-Delayed Domino for Adder and Combinational Logic Desig
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
High-Performance Asynchronous Pipeline Circuits
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Dynamic Logic in Four-Phase Micropipelines
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
A Fast Asynchronous Huffman Decoder for Compressed-Code Embedded Processors
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
An Asynchronous Low-Power 80C51 Microcontroller
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
RAPPID: An Asynchronous Instruction Length Decoder
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
High-Throughput Asynchronous Pipelines for Fine-Grain Dynamic Datapaths
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
AMULET3i - An Asynchronous System-on-Chip
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
High-Speed QDI Asynchronous Pipelines
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Synchronous Interlocked Pipelines
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
The Design of an Asynchronous MIPS R3000 Microprocessor
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
A doubly-latched asynchronous pipeline
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
High-Speed Non-Linear Asynchronous Pipelines
Proceedings of the conference on Design, automation and test in Europe
Single-Track Asynchronous Pipeline Templates Using 1-of-N Encoding
Proceedings of the conference on Design, automation and test in Europe
The design of high-throughput asynchronous pipelines
The design of high-throughput asynchronous pipelines
The design of high-performance dynamic asynchronous pipelines: high-capacity style
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Three generations of asynchronous microprocessors
IEEE Design & Test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Asynchronous data-driven circuit synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A low latency wormhole router for asynchronous on-chip networks
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
High-speed low-power multiplexer-based selector for priority policy
Computers and Electrical Engineering
Area efficient asynchronous SDM routers using 2-stage clos switches
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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A new class of asynchronous pipelines is proposed, called lookahead pipelines (LP), which use dynamic logic and are capable of delivering multi-gigahertz throughputs. Since they are asynchronous, these pipelines avoid problems related to high-speed clock distribution, such as clock power, management of clock skew, and inflexibility in handling varied environments. The designs are based on the well-known PSO style of Williams and Horowitz as a starting point, but achieve significant improvements through novel protocol optimizations: the pipeline communication is structured so that critical events can be detected and exploited earlier. A special focus of this work is to target extremely fine-grain or gate-level pipelines, where the datapath is sectioned into stages, each consisting of logic that is only a single level deep. Both dual-rail and single-rail pipeline implementations are proposed. All the implementations are characterized by low-cost control structures and the avoidance of explicit latches. Post-layout SPICE simulations, in 0.18-µm technology, indicate that the best dual-rail LP design has more than twice the throughput (1.04 giga data items/s) of Williams' PSO design, while the best single-rail LP design achieves even higher throughput (1.55 giga data items/s).