Practical advances in asynchronous design and in asynchronous/synchronous interfaces
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Statistically optimized asynchronous barrel shifters for variable length codecs
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Evaluation of a high performance code compression method
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Compiler techniques for code compaction
ACM Transactions on Programming Languages and Systems (TOPLAS)
A code decompression architecture for VLIW processors
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Reducing probabilistic timed petri nets for asynchronous architectural analysis
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Generation of fast interpreters for Huffman compressed bytecode
Proceedings of the 2003 workshop on Interpreters, virtual machines and emulators
Survey of code-size reduction methods
ACM Computing Surveys (CSUR)
LZW-Based Code Compression for VLIW Embedded Systems
Proceedings of the conference on Design, automation and test in Europe - Volume 3
RL-huffman encoding for test compression and power reduction in scan applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Efficient performance analysis of asynchronous systems based on periodicity
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Profile-driven compression scheme for embedded systems
Proceedings of the 3rd conference on Computing frontiers
Generation of fast interpreters for Huffman compressed bytecode
Science of Computer Programming - Special issue on advances in interpreters, virtual machines and emulators (IVME'03)
An efficient algorithm for time separation of events in concurrent systems
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
The design of high-performance dynamic asynchronous pipelines: lookahead style
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Code compression for VLIW embedded systems using a self-generating table
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Selective Code Compression Scheme for Embedded Systems
Transactions on High-Performance Embedded Architectures and Compilers I
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This paper presents the architecture and design of a high-performance asynchronous Huffman decoder for compressed-code embedded processors. In such processors, embedded programs are stored in compressed form in instruction ROM, then are decompressed on demand during instruction cache refill. The Huffman decoder is used as a code decompression engine. The circuit is non-pipelined, and is implemented as an iterative self-timed ring. It achieves a high-speed decode rate with very low area overhead. Simulations using Lsim show an average throughput of 32 bits/25 ns on the output side (or 163 MBytes/sec, or 1303 Mbit/sec), corresponding to about 889 Mbit/sec on the input side. The area of the design is extremely small: under 1 mm2 in a 0.8 micron full-custom layout. The decoder is estimated to have higher throughput than any comparable synchronous Huffman decoder (after normalizing for feature size and voltage), yet is much smaller than synchronous designs. Its performance is also 83% faster than a recently published asynchronous Huffman decoder using the same technology.