Dr. Dobb's Journal
Text compression
Executing compressed programs on an embedded RISC architecture
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Improving code density using compression techniques
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Compiler-driven cached code compression schemes for embedded ILP processors
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Code compression for VLIW processors using variable-to-fixed coding
Proceedings of the 15th international symposium on System Synthesis
A Fast Asynchronous Huffman Decoder for Compressed-Code Embedded Processors
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Code density optimization for embedded DSP processors using data compression techniques
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
A Simple and Fast Scheme for Code Compression for VLIW Processors
DCC '03 Proceedings of the Conference on Data Compression
Profile-Driven Selective Code Compression
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
SAMC: a code compression algorithm for embedded processors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Compiler-Guided data compression for reducing memory consumption of embedded applications
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Using Lin-Kernighan algorithm for look-up table compression to improve code density
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Journal of VLSI Signal Processing Systems
Adaptive object code compression
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Data compression algorithms for energy-constrained devices in delay tolerant networks
Proceedings of the 4th international conference on Embedded networked sensor systems
A bitmask-based code compression technique for embedded systems
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Efficient code density through look-up table compression
Proceedings of the conference on Design, automation and test in Europe
ASIP instruction encoding for energy and area reduction
Proceedings of the 44th annual Design Automation Conference
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Code compression for VLIW embedded systems using a self-generating table
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Access pattern-based code compression for memory-constrained systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
FBT: filled buffer technique to reduce code size for VLIW processors
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Dictionary-based program compression on customizable processor architectures
Microprocessors & Microsystems
Proceedings of the 46th Annual Design Automation Conference
Using data compression for increasing memory system utilization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Adaptive lossless compression in wireless body sensor networks
BodyNets '09 Proceedings of the Fourth International Conference on Body Area Networks
A universal placement technique of compressed instructions for efficient parallel decompression
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Compilation strategies for reducing code size on a VLIW processor with variable length instructions
HiPEAC'08 Proceedings of the 3rd international conference on High performance embedded architectures and compilers
Code density concerns for new architectures
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Code compression and decompression for coarse-grain reconfigurable architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient code compression for embedded processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Synergistic integration of code encryption and compression in embedded systems
Proceedings of the great lakes symposium on VLSI
Bitmask aware compression of NISC control words
Integration, the VLSI Journal
Prius: generic hybrid trace compression for wireless sensor networks
Proceedings of the 10th ACM Conference on Embedded Network Sensor Systems
| Hi-index | 0.00 |
We propose a new variable-sized-block method for VLIW code compression. Code compression traditionally works on fixed-sized blocks and its ef.ciency is limited by the smallblock size. Branch blocks -- instructions between two consecutive possible branch targets -- provide larger blocks for code compression. We propose LZW-based algorithms to compress branch blocks. Our approach is fully adaptive and generates coding table on-the-fly during compression and decompression. When encountering a branch target,the coding table is cleared to ensure correctness. Decompression requires only a simple lookup and update when necessary. Our method provides 8 bytes peak decompression bandwidth and 1.82 bytes in average. Compared to Huffman's 1 byte and V2F's 13-bit peak performance, our methods have higher decoding bandwidth and comparable compression ratio. Parallel decompression could also be applied to our methods, which is more suitable for VLIW architecture.