Text compression
Executing compressed programs on an embedded RISC architecture
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
An object code compression approach to embedded processors
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Improving code density using compression techniques
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Compiler-driven cached code compression schemes for embedded ILP processors
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Cached-code compression for energy minimization in embedded processors
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Decoding of Canonical Huffman Codes with Look-Up Tables
DCC '00 Proceedings of the Conference on Data Compression
LZW-Based Code Compression for VLIW Embedded Systems
Proceedings of the conference on Design, automation and test in Europe - Volume 3
A Unified Architecture for Adaptive Compression of Data and Code on Embedded Systems
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Dictionary Based Code Compression for Variable Length Instruction Encodings
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Using Lin-Kernighan algorithm for look-up table compression to improve code density
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
Automotive software and systems engineering
MEMOCODE '05 Proceedings of the 2nd ACM/IEEE International Conference on Formal Methods and Models for Co-Design
Instruction splitting for efficient code compression
Proceedings of the 44th annual Design Automation Conference
Access pattern-based code compression for memory-constrained systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Instruction re-encoding facilitating dense embedded code
Proceedings of the conference on Design, automation and test in Europe
FBT: filled buffer technique to reduce code size for VLIW processors
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A universal placement technique of compressed instructions for efficient parallel decompression
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Code density concerns for new architectures
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Huffman-based code compression techniques for embedded processors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Efficient code compression for embedded processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
MELOADES: Methodology for long-term online adaptation of embedded software for heterogeneous devices
Journal of Systems Architecture: the EUROMICRO Journal
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Code density is a major requirement in embedded system design since it not only reduces the need for the scarce resource memory but also implicitly improves further important design parameters like power consumption and performance. Within this paper we introduce a novel and efficient hardware-supported approach that belongs to the group of statistical compression schemes as it is based on Canonical Huffman Coding. In particular, our scheme is the first to also compress the necessary Look-up Tables that can become significant in size if the application is large and/or high compression is desired. Our scheme optimizes the number of generated Look-up Tables to improve the compression ratio. In average, we achieve compression ratios as low as 49% (already including the overhead of the Lookup Tables). Thereby, our scheme is entirely orthogonal to approaches that take particularities of a certain instruction set architecture into account. We have conducted evaluations using a representative set of applications and have applied it to three major embedded processor architectures, namely ARM, MIPS and PowerPC.