Text compression
Executing compressed programs on an embedded RISC architecture
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
An object code compression approach to embedded processors
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Improving code density using compression techniques
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
The SimpleScalar tool set, version 2.0
ACM SIGARCH Computer Architecture News
Instruction encoding techniques for area minimization of instruction ROM
Proceedings of the 11th international symposium on System synthesis
Compiler-driven cached code compression schemes for embedded ILP processors
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
A minimum spanning tree algorithm with inverse-Ackermann type complexity
Journal of the ACM (JACM)
Cached-code compression for energy minimization in embedded processors
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Space- and Time-Efficient Decoding with Canonical Huffman Trees
CPM '97 Proceedings of the 8th Annual Symposium on Combinatorial Pattern Matching
Code density optimization for embedded DSP processors using data compression techniques
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Decoding of Canonical Huffman Codes with Look-Up Tables
DCC '00 Proceedings of the Conference on Data Compression
DISE: a programmable macro engine for customizing applications
Proceedings of the 30th annual international symposium on Computer architecture
Hardware-Assisted Data Compression for Energy Minimization in Systems with Embedded Processors
Proceedings of the conference on Design, automation and test in Europe
LZW-Based Code Compression for VLIW Embedded Systems
Proceedings of the conference on Design, automation and test in Europe - Volume 3
A hamming distance based VLIW/EPIC code compression technique
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
A Unified Architecture for Adaptive Compression of Data and Code on Embedded Systems
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Dictionary Based Code Compression for Variable Length Instruction Encodings
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
A post-compilation register reassignment technique for improving hamming distance code compression
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Using Lin-Kernighan algorithm for look-up table compression to improve code density
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
Efficient code density through look-up table compression
Proceedings of the conference on Design, automation and test in Europe
Automotive software and systems engineering
MEMOCODE '05 Proceedings of the 2nd ACM/IEEE International Conference on Formal Methods and Models for Co-Design
Code compression for embedded VLIW processors using variable-to-fixed coding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SAMC: a code compression algorithm for embedded processors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multilevel Huffman Coding: An Efficient Test-Data Compression Method for IP Cores
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A universal placement technique of compressed instructions for efficient parallel decompression
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Code density is of increasing concern in embedded system design since it reduces the need for the scarce resource memory and also implicitly improves further important design parameters like power consumption and performance. In this paper we introduce a novel, hardware-supported approach. Besides the code, also the lookup tables (LUTs) are compressed, that can become significant in size if the application is large and/or high compression is desired. Our scheme optimizes the number and size of generated LUTs to improve the compression ratio. To show the efficiency of our approach, we apply it to two compression schemes: "dictionary-based" and "statistical". We achieve an average compression ratio of 48% (already including the overhead of the LUTs). Thereby, our scheme is orthogonal to approaches that take particularities of a certain instruction set architecture into account. We have conducted evaluations using a representative set of applications and have applied it to three major embedded processor architectures, namely ARM, MIPS, and PowerPC.