Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Executing compressed programs on an embedded RISC architecture
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
A Theory of Program Size Formally Identical to Information Theory
Journal of the ACM (JACM)
Data compression via textual substitution
Journal of the ACM (JACM)
Common phrases and minimum-space text storage
Communications of the ACM
The Art of Programming Embedded Systems
The Art of Programming Embedded Systems
Storage assignment to decrease code size
PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
Procedure based program compression
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Code compression for embedded systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
Instruction encoding techniques for area minimization of instruction ROM
Proceedings of the 11th international symposium on System synthesis
Enhanced code compression for embedded RISC processors
Proceedings of the ACM SIGPLAN 1999 conference on Programming language design and implementation
Compiler-driven cached code compression schemes for embedded ILP processors
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Proceedings of the 27th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Code compression as a variable in hardware/software co-design
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Code compression for low power embedded system design
Proceedings of the 37th Annual Design Automation Conference
Procedure Based Program Compression
International Journal of Parallel Programming - Special issue on the 30th annual ACM/IEEE international symposium on microarchitecture, part II
Design and simulation of a pipelined decompression architecture for embedded systems
Proceedings of the 14th international symposium on Systems synthesis
Design of an one-cycle decompression hardware for performance increase in embedded systems
Proceedings of the 39th annual Design Automation Conference
A code decompression architecture for VLIW processors
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Code compression for VLIW processors using variable-to-fixed coding
Proceedings of the 15th international symposium on System Synthesis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
CoCo: a hardware/software platform for rapid prototyping of code compression technologies
Proceedings of the 40th annual Design Automation Conference
Arithmetic Coding for Low Power Embedded System Design
DCC '00 Proceedings of the Conference on Data Compression
A Decompression Architecture for Low Power Embedded Systems
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Survey of code-size reduction methods
ACM Computing Surveys (CSUR)
LZW-Based Code Compression for VLIW Embedded Systems
Proceedings of the conference on Design, automation and test in Europe - Volume 3
High performance code compression architecture for the embedded ARM/THUMB processor
Proceedings of the 1st conference on Computing frontiers
Profile-driven compression scheme for embedded systems
Proceedings of the 3rd conference on Computing frontiers
Journal of VLSI Signal Processing Systems
FPGA-friendly code compression for horizontal microcoded custom IPs
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
A bitmask-based code compression technique for embedded systems
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Code size reduction by compressing repeated instruction sequences
The Journal of Supercomputing
Proceedings of the conference on Design, automation and test in Europe
Code compression for performance enhancement of variable-length embedded processors
ACM Transactions on Embedded Computing Systems (TECS)
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Code compression for VLIW embedded systems using a self-generating table
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Access pattern-based code compression for memory-constrained systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Selective Code Compression Scheme for Embedded Systems
Transactions on High-Performance Embedded Architectures and Compilers I
Compiler Support for Code Size Reduction Using a Queue-Based Processor
Transactions on High-Performance Embedded Architectures and Compilers II
Procedural Abstraction with Reverse Prefix Trees
Proceedings of the 7th annual IEEE/ACM International Symposium on Code Generation and Optimization
Code compression for embedded VLIW processors using variable-to-fixed coding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Approximate arithmetic coding for bus transition reduction in low power designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Code compression and decompression for coarse-grain reconfigurable architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient code compression for embedded processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimizing code size for embedded real-time applications
EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing
TinyVM: an energy-efficient execution infrastructure for sensor networks
Software—Practice & Experience
Bitmask aware compression of NISC control words
Integration, the VLSI Journal
Studying the code compression design space - A synthesis approach
Journal of Systems Architecture: the EUROMICRO Journal
| Hi-index | 0.00 |
We address the problem of code size minimization in VLSI systems with embedded DSP processors. Reducing code size reduces the production cost of embedded systems. We use data compression methods to develop code size minimization strategies. We present a framework for code size minimization where the compressed data consists of a dictionary and a skeleton. The dictionary can be computed using popular text compression algorithms. We describe two methods to execute the compressed code that have varying performance characteristics and varying degrees of freedom in compressing the code. Experimental results obtained with a TMS320C25 code generator are presented.