Text compression
Executing compressed programs on an embedded RISC architecture
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
An object code compression approach to embedded processors
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Profile-driven program synthesis for evaluation of system power dissipation
DAC '97 Proceedings of the 34th annual Design Automation Conference
Improving code density using compression techniques
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
A framework for estimation and minimizing energy dissipation of embedded HW/SW systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
Interface exploration for reduced power in core-based systems
Proceedings of the 11th international symposium on System synthesis
Power estimation for architectural exploration of HW/SW communication on system-level buses
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Stochastic modeling of a power-managed system: construction and optimization
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Selective instruction compression for memory energy reduction in embedded systems
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Code density optimization for embedded DSP processors using data compression techniques
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Random Access Decompression using Binary Arithmetic Coding
DCC '99 Proceedings of the Conference on Data Compression
Logic and system design for low power consumption
Logic and system design for low power consumption
A decompression core for powerPC
IBM Journal of Research and Development
Code compression as a variable in hardware/software co-design
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Profile-driven code execution for low power dissipation (poster session)
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Cached-code compression for energy minimization in embedded processors
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Design and simulation of a pipelined decompression architecture for embedded systems
Proceedings of the 14th international symposium on Systems synthesis
Tuning of loop cache architectures to programs in embedded system design
Proceedings of the 15th international symposium on System Synthesis
Application-driven processor design exploration for power-performance trade-off analysis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
ACM Transactions on Embedded Computing Systems (TECS)
Offline Data Profiling Techniques to Enhance Memory Compression in Embedded Systems
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Synthesis of customized loop caches for core-based embedded systems
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A DISE implementation of dynamic code decompression
Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems
Arithmetic Coding for Low Power Embedded System Design
DCC '00 Proceedings of the Conference on Data Compression
Input Space Adaptive Embedded Software Synthesis
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Approximate prefix coding for system-on-a-chip programs
Journal of Systems Architecture: the EUROMICRO Journal
Survey of code-size reduction methods
ACM Computing Surveys (CSUR)
Heap compression for memory-constrained Java environments
OOPSLA '03 Proceedings of the 18th annual ACM SIGPLAN conference on Object-oriented programing, systems, languages, and applications
Compiler optimization and ordering effects on VLIW code compression
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
IEEE Transactions on Computers
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Energy efficient code generation exploiting reduced bit-width instruction set architectures (rISA)
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Power Efficiency through Application-Specific Instruction Memory Transformations
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Low-power instruction bus encoding for embedded processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Access Pattern-Based Code Compression for Memory-Constrained Embedded Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
The implementation and evaluation of dynamic code decompression using DISE
ACM Transactions on Embedded Computing Systems (TECS)
Clustered Loop Buffer Organization for Low Energy VLIW Embedded Processors
IEEE Transactions on Computers
An Energy Efficient Instruction Set Synthesis Framework for Low Power Embedded System Designs
IEEE Transactions on Computers
Exploiting frequent field values in java objects for reducing heap memory requirements
Proceedings of the 1st ACM/USENIX international conference on Virtual execution environments
Design of a decompressor engine on a SPARC processor
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
CRAMES: compressed RAM for embedded systems
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Compilation framework for code size reduction using reduced bit-width ISAs (rISAs)
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Simultaneously improving code size, performance, and energy in embedded processors
Proceedings of the conference on Design, automation and test in Europe: Proceedings
High-quality ISA synthesis for low-power cache designs in embedded microprocessors
IBM Journal of Research and Development
High-performance operating system controlled memory compression
Proceedings of the 43rd annual Design Automation Conference
Energy-aware lossless data compression
ACM Transactions on Computer Systems (TOCS)
Journal of VLSI Signal Processing Systems
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Instruction buffering exploration for low energy embedded processors
Journal of Embedded Computing - Low-power Embedded Systems
Instruction trace compression for rapid instruction cache simulation
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
Code compression for performance enhancement of variable-length embedded processors
ACM Transactions on Embedded Computing Systems (TECS)
Access pattern-based code compression for memory-constrained systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Instruction re-encoding facilitating dense embedded code
Proceedings of the conference on Design, automation and test in Europe
COMPASS - A tool for evaluation of compression strategies for embedded processors
Journal of Systems Architecture: the EUROMICRO Journal
Quasistatic shared libraries and XIP for memory footprint reduction in MMU-less embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Selective Code Compression Scheme for Embedded Systems
Transactions on High-Performance Embedded Architectures and Compilers I
MEMMU: Memory expansion for MMU-less embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
HitME: low power Hit MEmory buffer for embedded systems
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Energy and performance evaluation of lossless file data compression on server systems
SYSTOR '09 Proceedings of SYSTOR 2009: The Israeli Experimental Systems Conference
An efficient segmental bus-invert coding method for instruction memory data bus switching reduction
EURASIP Journal on Embedded Systems
A universal placement technique of compressed instructions for efficient parallel decompression
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Online memory compression for embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
High-performance operating system controlled online memory compression
ACM Transactions on Embedded Computing Systems (TECS)
Minimizing area costs in GPS applications on a programmable DSP by code compression
SOC'09 Proceedings of the 11th international conference on System-on-chip
Journal of Systems Architecture: the EUROMICRO Journal
Huffman-based code compression techniques for embedded processors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
GPH: A group-based partitioning scheme for reducing total power consumption of parallel buses
Microprocessors & Microsystems
On the interplay of loop caching, code compression, and cache configuration
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Approximate arithmetic coding for bus transition reduction in low power designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Memory energy minimization by data compression: algorithms, architectures and implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
Study on LZW algorithm for embedded instruction memory
IMCAS'06 Proceedings of the 5th WSEAS international conference on Instrumentation, measurement, circuits and systems
Embedded Systems Design
Studying the code compression design space - A synthesis approach
Journal of Systems Architecture: the EUROMICRO Journal
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We propose instruction code compression as an efficient method for reducing power on an embedded system. Our approach is the first one to measure and optimize the power consumption of a complete SOC (System--On--a--Chip) comprising a CPU, instruction cache, data cache, main memory, data buses and address bus through code compression. We compare the pre-cache architecture (decompressor between main memory and cache) to a novel post-cache architecture (decompressor between cache and CPU). Our simulations and synthesis results show that our methodology results in large energy savings between 22% and 82% compared to the same system without code compression. Furthermore, we demonstrate that power savings come with reduced chip area and the same or even improved performance.