Data compression using dynamic Markov modelling
The Computer Journal
Text compression
Executing compressed programs on an embedded RISC architecture
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Arithmetic coding for data compression
Communications of the ACM
Improving code density using compression techniques
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Instruction encoding techniques for area minimization of instruction ROM
Proceedings of the 11th international symposium on System synthesis
Code compression for low power embedded system design
Proceedings of the 37th Annual Design Automation Conference
Code density optimization for embedded DSP processors using data compression techniques
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Random Access Decompression using Binary Arithmetic Coding
DCC '99 Proceedings of the Conference on Data Compression
Code compression as a variable in hardware/software co-design
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Survey of code-size reduction methods
ACM Computing Surveys (CSUR)
IEEE Transactions on Computers
Journal of VLSI Signal Processing Systems
Low power light-weight embedded systems
Proceedings of the 2006 international symposium on Low power electronics and design
Selective Code Compression Scheme for Embedded Systems
Transactions on High-Performance Embedded Architectures and Compilers I
Approximate arithmetic coding for bus transition reduction in low power designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We present a novel algorithm that assigns codes to instructions during instruction code compression in order to minimize bus-related bit toggling and thus reducing power consumption. The target application area is embedded systems, where power consumption is increasingly becoming a dominant design constraint.Our algorithm is based on a variant of quasi-arithmetic coding where coding allows for random access and fast table-based decoding. We take advantage of the approximations introduced to modify codes and reduce bit toggling, while maintaining compression performance and decoding speed.We present the first work to explore the trade-offs between compression ratios and bus-related power consumption and show that high compression ratios do not necessarily result in the lowest power consumption. By using our method, bus-related power consumption has been reduced by as much as 35% without imposing any additional hardware costs.