Text compression
Executing compressed programs on an embedded RISC architecture
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
An object code compression approach to embedded processors
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Improving code density using compression techniques
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
A framework for estimation and minimizing energy dissipation of embedded HW/SW systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
Instruction encoding techniques for area minimization of instruction ROM
Proceedings of the 11th international symposium on System synthesis
Selective instruction compression for memory energy reduction in embedded systems
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Code compression for low power embedded system design
Proceedings of the 37th Annual Design Automation Conference
Code density optimization for embedded DSP processors using data compression techniques
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Random Access Decompression using Binary Arithmetic Coding
DCC '99 Proceedings of the Conference on Data Compression
Arithmetic Coding for Low Power Embedded System Design
DCC '00 Proceedings of the Conference on Data Compression
A decompression core for powerPC
IBM Journal of Research and Development
SystemC
Survey of code-size reduction methods
ACM Computing Surveys (CSUR)
IEEE Transactions on Computers
Access Pattern-Based Code Compression for Memory-Constrained Embedded Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Access pattern-based code compression for memory-constrained systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
| Hi-index | 0.00 |
We present a new way to practice and view handware/software co-design: rather than raising the level of abstraction in order to exploit the highest possible degree of optimization, we use code compression i.e. we practice co-design at the bit-level. Through our novel architecture combined with our compression methodology this results in optimization of all major design goals/constraints. In particular, we present a compression methodology that deploys what we call a “post-cache architecture” (i.e. the detached decompression unit is located between the CPU and the instruction cache). We present a design methodology that allows the designer to control parameters like speed, power, and area through the choice of compression parameters. In addition we show that our compression methodology (using a Markov Model) is more efficient than the widely used Huffman compression scheme.