Evaluation of a high performance code compression method
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Code compression as a variable in hardware/software co-design
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
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Proceedings of the 37th Annual Design Automation Conference
HW/SW partitioning of an embedded instruction memory decompressor
Proceedings of the ninth international symposium on Hardware/software codesign
Combining Global Code and Data Compaction
OM '01 Proceedings of the 2001 ACM SIGPLAN workshop on Optimization of middleware and distributed systems
Design and simulation of a pipelined decompression architecture for embedded systems
Proceedings of the 14th international symposium on Systems synthesis
Heads and tails: a variable-length instruction format supporting parallel fetch and decode
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
Profile-guided code compression
PLDI '02 Proceedings of the ACM SIGPLAN 2002 Conference on Programming language design and implementation
A code decompression architecture for VLIW processors
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Code compression for VLIW processors using variable-to-fixed coding
Proceedings of the 15th international symposium on System Synthesis
Sifting out the mud: low level C++ code reuse
OOPSLA '02 Proceedings of the 17th ACM SIGPLAN conference on Object-oriented programming, systems, languages, and applications
The performance advantage of applying compression to the memory system
Proceedings of the 2002 workshop on Memory system performance
A DISE implementation of dynamic code decompression
Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems
Generation of fast interpreters for Huffman compressed bytecode
Proceedings of the 2003 workshop on Interpreters, virtual machines and emulators
Survey of code-size reduction methods
ACM Computing Surveys (CSUR)
Variable Instruction Set Architecture and Its Compiler Support
IEEE Transactions on Computers
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Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Class-Based Decompressor Design for Compressed Instruction Memory in Embedded Processors
IEEE Transactions on Computers
Compact Binaries with Code Compression in a Software Dynamic Translator
Proceedings of the conference on Design, automation and test in Europe - Volume 2
High performance code compression architecture for the embedded ARM/THUMB processor
Proceedings of the 1st conference on Computing frontiers
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IBM Journal of Research and Development
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IBM Journal of Research and Development
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DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
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ACM Transactions on Embedded Computing Systems (TECS)
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Proceedings of the 2nd conference on Computing frontiers
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Link-time binary rewriting techniques for program compaction
ACM Transactions on Programming Languages and Systems (TOPLAS)
Post-compilation optimization for multiple gains with pattern matching
ACM SIGPLAN Notices
A Self Test Program Design Technique for Embedded DSP Cores
Journal of Electronic Testing: Theory and Applications
Journal of VLSI Signal Processing Systems
Adaptive object code compression
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Generation of fast interpreters for Huffman compressed bytecode
Science of Computer Programming - Special issue on advances in interpreters, virtual machines and emulators (IVME'03)
Link-time compaction and optimization of ARM executables
ACM Transactions on Embedded Computing Systems (TECS)
FPGA-friendly code compression for horizontal microcoded custom IPs
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Automated reduction of the memory footprint of the Linux kernel
ACM Transactions on Embedded Computing Systems (TECS) - Special Section LCTES'05
Fragment cache management for dynamic binary translators in embedded systems with scratchpad
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
Code compression for performance enhancement of variable-length embedded processors
ACM Transactions on Embedded Computing Systems (TECS)
Merged Dictionary Code Compression for FPGA Implementation of Custom Microcoded PEs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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ACM Transactions on Design Automation of Electronic Systems (TODAES)
FBT: filled buffer technique to reduce code size for VLIW processors
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Algorithms and data structures for compressed-memory machines
IBM Journal of Research and Development
Code compression for embedded VLIW processors using variable-to-fixed coding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Approximate arithmetic coding for bus transition reduction in low power designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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ICESS'04 Proceedings of the First international conference on Embedded Software and Systems
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Code size efficiency is a critical parameter in the design of computer systems for embedded applications. This paper describes a method for improving code size efficiency involving the use of compression techniques to reduce the size of the stored code, and on-the-fly hardware decompression at full processor speed for execution. A simple frequency-based encoding scheme for PowerPC® code achieves a typical code size reduction to 60% of the original size. A corresponding decompression core has been implemented for an embedded microprocessor, such as the PowerPC 401TM. The compression/decompression scheme operates in a manner transparent to the processor and requires no changes to such tools as compilers, linkers, and loaders.