Text compression
Executing compressed programs on an embedded RISC architecture
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Improving code density using compression techniques
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Code compression for embedded systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
Design of an one-cycle decompression hardware for performance increase in embedded systems
Proceedings of the 39th annual Design Automation Conference
Code density optimization for embedded DSP processors using data compression techniques
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
A decompression core for powerPC
IBM Journal of Research and Development
CRAMES: compressed RAM for embedded systems
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Using Lin-Kernighan algorithm for look-up table compression to improve code density
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Quasistatic shared libraries and XIP for memory footprint reduction in MMU-less embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Online memory compression for embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
High-performance operating system controlled online memory compression
ACM Transactions on Embedded Computing Systems (TECS)
Code density concerns for new architectures
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
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The use of code compression in embedded systems based on standard RISC instruction set architectures (ISA) has been shown in the past to be of benefit in reducing overall system cost. The 16-bit THUMB ISA from ARM Ltd has a significantly higher density than the original 32-bits ARM ISA. Our proposed memory compression architecture has showed a further size reduction of 15% to 20% on the THUMB code. In this paper we propose to use a high-speed data lossless hardware decompressor to improve the timing performance of the architecture. We simulated the architecture on the SimpleScalar platform and show that for some applications, the time overheads are limited within 5% of the original application.