Text compression
Executing compressed programs on an embedded RISC architecture
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
An object code compression approach to embedded processors
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Instruction encoding techniques for area minimization of instruction ROM
Proceedings of the 11th international symposium on System synthesis
Selective instruction compression for memory energy reduction in embedded systems
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Code density optimization for embedded DSP processors using data compression techniques
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Variable Instruction Set Architecture and Its Compiler Support
IEEE Transactions on Computers
High performance code compression architecture for the embedded ARM/THUMB processor
Proceedings of the 1st conference on Computing frontiers
Multi-profile based code compression
Proceedings of the 41st annual Design Automation Conference
Energy efficient code generation exploiting reduced bit-width instruction set architectures (rISA)
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Profile-Driven Selective Code Compression
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A software-only compression system for trading-offs between performance and code size
SCOPES '05 Proceedings of the 2005 workshop on Software and compilers for embedded systems
Adaptive and flexible dictionary code compression for embedded applications
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Data compression algorithms for energy-constrained devices in delay tolerant networks
Proceedings of the 4th international conference on Embedded networked sensor systems
A bitmask-based code compression technique for embedded systems
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Proceedings of the conference on Design, automation and test in Europe
Instruction splitting for efficient code compression
Proceedings of the 44th annual Design Automation Conference
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
Merged Dictionary Code Compression for FPGA Implementation of Custom Microcoded PEs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Bitmask-based control word compression for NISC architectures
Proceedings of the 19th ACM Great Lakes symposium on VLSI
A universal placement technique of compressed instructions for efficient parallel decompression
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Minimizing area costs in GPS applications on a programmable DSP by code compression
SOC'09 Proceedings of the 11th international conference on System-on-chip
Code compression for embedded VLIW processors using variable-to-fixed coding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An approach for code compression in run time for embedded systems: a preliminary results
ICA3PP'11 Proceedings of the 11th international conference on Algorithms and architectures for parallel processing - Volume Part I
Microprocessors & Microsystems
Bitmask aware compression of NISC control words
Integration, the VLSI Journal
Prius: generic hybrid trace compression for wireless sensor networks
Proceedings of the 10th ACM Conference on Embedded Network Sensor Systems
Studying the code compression design space - A synthesis approach
Journal of Systems Architecture: the EUROMICRO Journal
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Code compression is known as an effective technique to reduce instruction memory size on an embedded system. However, code compression can also be very effective in increasing processor-to-memory bandwidth and hence provide increased system performance. In this paper we describe our design and design methodology of the first running prototype of a one-cycle code decompression unit that decompresses compressed instructions on-the-fly. We describe in detail the architecture that enables decompression of multiple instructions in one cycle and we present the design methodologies and tools used. The stand-alone decompression unit does not require any modifications on the processor core. We observed up to 63% performance increase with 25% in average over a wide variety of applications running on the hardware prototype under various system configurations.