Executing compressed programs on an embedded RISC architecture
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Improving code density using compression techniques
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Code compression for embedded systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
Selective instruction compression for memory energy reduction in embedded systems
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Design of an one-cycle decompression hardware for performance increase in embedded systems
Proceedings of the 39th annual Design Automation Conference
A Simple and Fast Scheme for Code Compression for VLIW Processors
DCC '03 Proceedings of the Conference on Data Compression
IEEE Transactions on Computers
Multi-profile based code compression
Proceedings of the 41st annual Design Automation Conference
A hamming distance based VLIW/EPIC code compression technique
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
RTCSA '05 Proceedings of the 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications
A bitmask-based code compression technique for embedded systems
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
Minimizing memory access energy in embedded systems by selective instruction compression
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SAMC: a code compression algorithm for embedded processors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Bitmask-Based Code Compression for Embedded Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In recent years, code compression has been frequently investigated for embedded systems to reduce memory use and power consumption. Among various compression schemes, dictionary-based ones are applied for their good compression ratios and rapid decompression engines. Bitmask-based code compression, which was derived from the dictionary-based ones, has been proven to have a superior compression ratio and rapid decompression engine. In this paper, we adopt the bitmask-based scheme and replace some of its dictionary entries to achieve greatly reduced power consumption while maintaining a competitive compression ratio. For a cacheless architecture, we propose three basic styles of replacement, namely by-access-saving, by-frequency, and by-block. Another procedure, called by-alignment, is applied afterward to further improve power consumption. According to the experimental results, the by-block scheme with the by-alignment procedure achieves the best result. In the best case, an increase of 1.61% in compression ratio can result in a 43.75% reduction in power consumption ratio.