Text compression
Executing compressed programs on an embedded RISC architecture
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
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OSDI '96 Proceedings of the second USENIX symposium on Operating systems design and implementation
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MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
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FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
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ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
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CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
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DCC '00 Proceedings of the Conference on Data Compression
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FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
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ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
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ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Compressed Code Execution on DSP Architectures
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Journal of Systems Architecture: the EUROMICRO Journal
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Survey of code-size reduction methods
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Variable Instruction Set Architecture and Its Compiler Support
IEEE Transactions on Computers
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LZW-Based Code Compression for VLIW Embedded Systems
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Multi-profile based code compression
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A New Algorithm for Energy-Driven Data Compression in VLIW Embedded Processors
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
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Code compression by register operand dependency
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Dynamic coalescing for 16-bit instructions
ACM Transactions on Embedded Computing Systems (TECS)
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A post-compilation register reassignment technique for improving hamming distance code compression
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A bitmask-based code compression technique for embedded systems
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The Journal of Supercomputing
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Journal of Systems Architecture: the EUROMICRO Journal
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IEEE Transactions on Software Engineering
Instruction splitting for efficient code compression
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ACM Transactions on Embedded Computing Systems (TECS)
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Transactions on High-Performance Embedded Architectures and Compilers I
Dictionary-based program compression on customizable processor architectures
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Bitmask-based control word compression for NISC architectures
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SAS'03 Proceedings of the 10th international conference on Static analysis
Huffman-based code compression techniques for embedded processors
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Two versions of architectures for dynamic implied addressing mode
Journal of Systems Architecture: the EUROMICRO Journal
Configuration compression for FPGA-based embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Study on LZW algorithm for embedded instruction memory
IMCAS'06 Proceedings of the 5th WSEAS international conference on Instrumentation, measurement, circuits and systems
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient code compression for embedded processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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ACM Transactions on Architecture and Code Optimization (TACO)
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Optimizing code size for embedded real-time applications
EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing
A new technique for program code compression in embedded microprocessor
ICESS'04 Proceedings of the First international conference on Embedded Software and Systems
Microprocessors & Microsystems
Extrinsic and intrinsic text cloning
ISCA'10 Proceedings of the 2010 international conference on Computer Architecture
Bitmask aware compression of NISC control words
Integration, the VLSI Journal
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ACM Transactions on Design Automation of Electronic Systems (TODAES)
Microcode Compression Using Structured-Constrained Clustering
International Journal of Parallel Programming
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We propose a method for compressing programs in embedded processors where instruction memory size dominates cost. A post-compilation analyzer examines a program and replaces common sequences of instructions with a single instruction codeword. A microprocessor executes the compressed instruction sequences by fetching code words from the instruction memory, expanding them back to the original sequence of instructions in the decode stage, and issuing them to the execution stages. We apply our technique to the PowerPC, ARM, and i386 instruction sets and achieve an average size reduction of 39%, 34%, and 26%, respectively, for SPEC CINT95 programs.