Executing compressed programs on an embedded RISC architecture
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
The SPARC architecture manual (version 9)
The SPARC architecture manual (version 9)
Storage assignment to decrease code size
ACM Transactions on Programming Languages and Systems (TOPLAS)
Improving code density using compression techniques
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Enhanced code compression for embedded RISC processors
Proceedings of the ACM SIGPLAN 1999 conference on Programming language design and implementation
Preliminary design examination of the ParalleX system from a software and hardware perspective
ACM SIGMETRICS Performance Evaluation Review - Special issue on the 1st international workshop on performance modeling, benchmarking and simulation of high performance computing systems (PMBS 10)
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Instruction pressure is the level of time, space, and power required to manage the instruction stream to support high-speed execution of modern multicore general processor and embedded controller based computing. L1 instruction cache and processor pin bandwidth are examples of direct resource costs imposed by the instruction access demand of a processor architecture. This paper explores the potential for reducing instruction pressure through a combination of variable length binary instruction set and Huffman encoding to reduce the average number of bits per instruction compared to a typical fixed-length fixed-code binary instruction set. The PRECISE (Processor Register Extensions for Collapsed Instruction Set Encoding) methodology addresses the data type, opcode, and register access components of the instruction stream. This paper focuses on opcode compression through a set of benchmark-driven experiments to identify clusters of near optimal ISA fits. The results demonstrate that a small number of distinct binary ISAs can provide reasonably good fits across a broad range of application benchmarks.