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The Design of an Optimizing Compiler
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Combining Global Code and Data Compaction
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PLDI '02 Proceedings of the ACM SIGPLAN 2002 Conference on Programming language design and implementation
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Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
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Generation of fast interpreters for Huffman compressed bytecode
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ACM Transactions on Embedded Computing Systems (TECS)
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ACM Transactions on Embedded Computing Systems (TECS)
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Clone detection via structural abstraction
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CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Code compaction of matching single-entry multiple-exit regions
SAS'03 Proceedings of the 10th international conference on Static analysis
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Code compression for embedded VLIW processors using variable-to-fixed coding
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ACM Transactions on Architecture and Code Optimization (TACO)
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Extrinsic and intrinsic text cloning
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Software—Practice & Experience
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This paper explores compiler techniques for reducing the memory needed to load and run program executables. In embedded systems, where economic incentives to reduce both RAM and ROM are strong, the size of compiled code is increasingly important. Similarly, in mobile and network computing, the need to transmit an executable before running it places a premium on code size. Our work focuses on reducing the size of a program's code segment, using pattern-matching techniques to identify and coalesce together repeated instruction sequences. In contrast to other methods, our framework preserves the ability to run program executables directly, without an intervening decompression stage. Our compression framework is integrated into an industrial-strength optimizing compiler, which allows us to explore the interaction between code compression and classical code optimization techniques, and requires that we contend with the difficulties of compressing previously optimized code. The specific contributions in this paper include a comprehensive experimental evaluation of code compression for a RISC-like architecture, a more powerful pattern-matching scheme for improved identification of repeated code fragments, and a new form of profile-driven code compression that reduces the speed penalty arising from compression.