Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
The priority-based coloring approach to register allocation
ACM Transactions on Programming Languages and Systems (TOPLAS)
Register allocation via hierarchical graph coloring
PLDI '91 Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation
Executing compressed programs on an embedded RISC architecture
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Load/store range analysis for global register allocation
PLDI '93 Proceedings of the ACM SIGPLAN 1993 conference on Programming language design and implementation
Improvements to graph coloring register allocation
ACM Transactions on Programming Languages and Systems (TOPLAS)
Storage assignment to decrease code size
ACM Transactions on Programming Languages and Systems (TOPLAS)
Spill code minimization via interference region spilling
Proceedings of the ACM SIGPLAN 1997 conference on Programming language design and implementation
Proceedings of the ACM SIGPLAN 1997 conference on Programming language design and implementation
The design and implementation of RAP: a PDG-based register allocator
Software—Practice & Experience
Storage assignment optimizations to generate compact and efficient code on embedded DSPs
Proceedings of the ACM SIGPLAN 1999 conference on Programming language design and implementation
Enhanced code compression for embedded RISC processors
Proceedings of the ACM SIGPLAN 1999 conference on Programming language design and implementation
Optimizing for reduced code space using genetic algorithms
Proceedings of the ACM SIGPLAN 1999 workshop on Languages, compilers, and tools for embedded systems
Analyzing and compressing assembly code
SIGPLAN '84 Proceedings of the 1984 SIGPLAN symposium on Compiler construction
A New Framework for Integrated Global Local Scheduling
PACT '98 Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques
Extending the applicability of scalar replacement to multiple induction variables
LCPC'04 Proceedings of the 17th international conference on Languages and Compilers for High Performance Computing
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Spill code generated during register allocation greatly influences the overall quality of compiled code, both in terms of speed as well as size. In embedded systems, where size of memory is often a major constraint, the size of compiled code is very important. In this paper we present a framework for better generation and placement of spill code for RISC-style embedded processors. Our framework attempts to achieve efficient execution and reduce spill-induced code growth. Traditional graph-coloring allocators often make spilling decisions which are not guided by program structure or path-sensitive control flow information. Quite often, allocation decisions get heavily influenced by the choice of candidates for register residency. Especially for systems with a limited number of registers, if one is not careful to contain register pressure, it could lead to generation of a lot of spill code. We propose a framework which selectively demotes variables in a contained manner and influences the formation of live ranges. The decisions for selective demotion are made through a flow-analytic approach such that fewer spill instructions are generated. Our approach tries to keep variables as candidates for register allocation only along the paths where it is profitable to do so. We attempt to identify good local candidates for demotion, however, decisions are taken only after their global demotion costs are captured. We have implemented our framework inside the SGI MIPSPRO compiler. Our results show improvement over a Briggs-style allocator in reducing code size upto 3:5% and upto 8:2% in reducing static loads in some cases for a register set of size 8. The results are very encouraging for other parameters as well for various sizes of register sets.