Optimizing stack frame accesses for processors with restricted addressing modes
Software—Practice & Experience
Storage assignment to decrease code size
PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
Optimal code generation for embedded memory non-homogeneous register architectures
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Memory bank and register allocation in software synthesis for ASIPs
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Storage assignment to decrease code size
ACM Transactions on Programming Languages and Systems (TOPLAS)
Optimal register assignment to loops for embedded code generation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Using register-transfer paths in code generation for heterogeneous memory-register architectures
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Algorithms for address assignment in DSP code generation
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Analysis and evaluation of address arithmetic capabilities in custom DSP architectures
DAC '97 Proceedings of the 34th annual Design Automation Conference
The Generation of Optimal Code for Arithmetic Expressions
Journal of the ACM (JACM)
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
The theory of parsing, translation, and compiling
The theory of parsing, translation, and compiling
Non-local Instruction Scheduling with Limited Code Growth
LCTES '98 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems
Optimization of Embedded DSP Programs Using Post-Pass Data-Flow Analysis
ICASSP '97 Proceedings of the 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '97) -Volume 1 - Volume 1
Instruction Set Design and Optimizations for Address Computation in DSP Architectures
ISSS '96 Proceedings of the 9th international symposium on System synthesis
Code generation and optimization for embedded digital signal processors
Code generation and optimization for embedded digital signal processors
Minimizing cost of local variables access for DSP-processors
Proceedings of the ACM SIGPLAN 1999 workshop on Languages, compilers, and tools for embedded systems
Proceedings of the 27th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Register allocation for common subexpressions in DSP data paths
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Code generation for embedded processors
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Storage allocation for embedded processors
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
Exploiting prolific types for memory management and optimizations
POPL '02 Proceedings of the 29th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Compiling with code-size constraints
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
Address assignment combined with scheduling in DSP code generation
Proceedings of the 39th annual Design Automation Conference
Global array reference allocation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Improving Offset Assignment on Embedded Processors Using Transformations
HiPC '00 Proceedings of the 7th International Conference on High Performance Computing
Improving Offset Assignment for Embedded Processors
LCPC '00 Proceedings of the 13th International Workshop on Languages and Compilers for Parallel Computing-Revised Papers
A Framework for Enhancing Code Quality in Limited Register Set Embedded Processors
LCTES '00 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems
Array Reference Allocation Using SSA-Form and Live Range Growth
LCTES '00 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems
Proceedings of the 40th annual Design Automation Conference
Storage assignment optimizations through variable coalescence for embedded processors
Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems
Simple offset assignment in presence of subword data
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Efficient spill code for SDRAM
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Compiling with code-size constraints
ACM Transactions on Embedded Computing Systems (TECS)
Power-efficient prefetching via bit-differential offset assignment on embedded processors
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Optimizing Address Code Generation for Array-Intensive DSP Applications
Proceedings of the international symposium on Code generation and optimization
An ILP based approach to address code generation for digital signal processors
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Reducing code size through address register assignment
ACM Transactions on Embedded Computing Systems (TECS)
ACM Transactions on Programming Languages and Systems (TOPLAS)
Offset assignment using simultaneous variable coalescing
ACM Transactions on Embedded Computing Systems (TECS)
Power-efficient prefetching for embedded processors
ACM Transactions on Embedded Computing Systems (TECS)
A new heuristic for SOA problem based on effective tie break function
SCOPES '08 Proceedings of the 11th international workshop on Software & compilers for embedded systems
Memory Offset Assignment for DSPs
ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
An optimization framework for embedded processors with auto-addressing mode
ACM Transactions on Programming Languages and Systems (TOPLAS)
An efficient code update scheme for DSP applications in mobile embedded systems
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems
Usability evaluation of Korean e-government portal
UAHCI'07 Proceedings of the 4th international conference on Universal access in human-computer interaction: applications and services
Evaluation of offset assignment heuristics
HiPEAC'07 Proceedings of the 2nd international conference on High performance embedded architectures and compilers
Address register assignment for reducing code size
CC'03 Proceedings of the 12th international conference on Compiler construction
Evaluating address register assignment and offset assignment algorithms
ACM Transactions on Embedded Computing Systems (TECS)
Exploiting parallelism in memory operations for code optimization
LCPC'04 Proceedings of the 17th international conference on Languages and Compilers for High Performance Computing
Storage Optimization through Offset Assignment with Variable Coalescing
ACM Transactions on Embedded Computing Systems (TECS)
An ILP solution to address code generation for embedded applications on digital signal processors
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
On Heuristic Solutions to the Simple Offset Assignment Problem in Address-Code Optimization
ACM Transactions on Embedded Computing Systems (TECS)
Minimizing address arithmetic instructions in embedded applications on DSPs
Computers and Electrical Engineering
Solving the simple offset assignment problem as a traveling salesman
Proceedings of the 16th International Workshop on Software and Compilers for Embedded Systems
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DSP architectures typically provide dedicated memory address generation units and indirect addressing modes with auto-increment and auto-decrement that subsume address arithmetic calculation. The heavy use of auto-increment and auto-decrement indirect addressing require DSP compilers to perform a careful placement of variables in storage to minimize address arithmetic instructions to generate compact and efficient DSP code. Liao et al. formulated the problem of storage assignment as the simple offset assignment problem (SOA) and the general offset assignment problem (GOA), and proposed heuristic solutions.The storage allocation of variables critically depends on the sequence of variable accesses. In this paper we present techniques to optimize the access sequence of variables by applying algebraic transformations (such as commutativity and associativity) on expression trees to obtain the least cost offset assignment. We develop a new formulation of this problem as the least cost access sequence problem (LCAS). Based on the proposed framework, we develop heuristic algorithms that determine empirically near-optimal solutions resulting in fewer address arithmetic instructions. We have implemented the proposed heuristic algorithms by extending the storage assignment optimization in the SPAM compiler back-end targeted for the TMS320C25 DSP. In the case of SOA, experimental results for programs from the DSPstone benchmark suite show an average improvement of 3.36% in static code size and an average relative speed-up of 7.28% over results obtained using existing SOA algorithms. The average code size reduction over code compiled with a naive storage assignment algorithm is 7.04%. The proposed framework has also been applied to the GOA problem and shows average code size reductions of 2.04% over results obtained using existing GOA algorithms, and average code size reductions of 10.84% over a naive GOA algorithm. Code size reduction and improvement in dynamic instruction counts could be valuable given limited memory and real-time response requirements placed on embedded systems.