Storage assignment to decrease code size
ACM Transactions on Programming Languages and Systems (TOPLAS)
Algorithms for address assignment in DSP code generation
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
DSP address optimization using a minimum cost circulation technique
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
A uniform optimization technique for offset assignment problems
Proceedings of the 11th international symposium on System synthesis
Addressing optimization for loop execution targeting DSP with auto-increment/decrement architecture
Proceedings of the 11th international symposium on System synthesis
Storage assignment optimizations to generate compact and efficient code on embedded DSPs
Proceedings of the ACM SIGPLAN 1999 conference on Programming language design and implementation
Scheduling-based code size reduction in processors with indirect addressing mode
Proceedings of the ninth international symposium on Hardware/software codesign
Improving Offset Assignment for Embedded Processors
LCPC '00 Proceedings of the 13th International Workshop on Languages and Compilers for Parallel Computing-Revised Papers
Storage assignment optimizations through variable coalescence for embedded processors
Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems
Code generation and optimization for embedded digital signal processors
Code generation and optimization for embedded digital signal processors
Optimizing Address Code Generation for Array-Intensive DSP Applications
Proceedings of the international symposium on Code generation and optimization
An ILP based approach to address code generation for digital signal processors
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
Offset assignment using simultaneous variable coalescing
ACM Transactions on Embedded Computing Systems (TECS)
Address register assignment for reducing code size
CC'03 Proceedings of the 12th international conference on Compiler construction
Offset assignment showdown: evaluation of DSP address code optimization algorithms
CC'03 Proceedings of the 12th international conference on Compiler construction
Address assignment in DSP code generation - an integrated approach
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Solving the simple offset assignment problem as a traveling salesman
Proceedings of the 16th International Workshop on Software and Compilers for Embedded Systems
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In digital signal processors (DSPs), variables are accessed using k address registers. The problem of finding a memory layout, for a set of variables, that minimizes the address-computation overhead is known as the General Offset Assignment (GOA) problem. The most common approach to this problem is to partition the set of variables into k partitions and to assign each partition to an address register. Thus, effectively decomposing the GOA problem into several Simple Offset Assignment (SOA) problems. Many heuristic-based algorithms are proposed in the literature to approximate solutions to both the variable partitioning and the SOA problems. However, the address-computation overhead of the resulting memory layouts are not accurately evaluated. This article presents an evaluation of memory layouts that uses Gebotys' optimal address-code generation technique. The use of this evaluation method leads to a new optimization problem: the Memory Layout Permutation (MLP) problem. We then use Gebotys' technique and an exhaustive solution to the MLP problem to evaluate heuristic-based offset-assignment algorithms. The memory layouts produced by each algorithm are compared against each other and against the optimal layouts. The results show that even in small access sequences with 12 variables or less, current heuristics may produce memory layouts with address-computation overheads up to two times higher than the overhead of an optimal layout.