Power analysis of embedded software: a first step towards software power minimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Storage assignment to decrease code size
PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
Address calculation for retargetable compilation and exploration of instruction-set architectures
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Algorithms for address assignment in DSP code generation
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Power exploration for data dominated video applications
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
An efficient model for DSP code generation: performance, code size, estimated energy
ISSS '97 Proceedings of the 10th international symposium on System synthesis
Code Generation for Embedded Processors
Code Generation for Embedded Processors
An efficient model for DSP code generation: performance, code size, estimated energy
ISSS '97 Proceedings of the 10th international symposium on System synthesis
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
A uniform optimization technique for offset assignment problems
Proceedings of the 11th international symposium on System synthesis
Address code generation for digital signal processors
Proceedings of the 38th annual Design Automation Conference
Proceedings of the 14th international symposium on Systems synthesis
Address assignment combined with scheduling in DSP code generation
Proceedings of the 39th annual Design Automation Conference
Global array reference allocation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Readings in hardware/software co-design
Array Reference Allocation Using SSA-Form and Live Range Growth
LCTES '00 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems
Optimal Live Range Merge for Address Register Allocation in Embedded Programs
CC '01 Proceedings of the 10th International Conference on Compiler Construction
Storage assignment optimizations through variable coalescence for embedded processors
Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems
Address code generation for DSP instruction-set architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Optimizing Address Code Generation for Array-Intensive DSP Applications
Proceedings of the international symposium on Code generation and optimization
An optimization framework for embedded processors with auto-addressing mode
ACM Transactions on Programming Languages and Systems (TOPLAS)
Evaluation of offset assignment heuristics
HiPEAC'07 Proceedings of the 2nd international conference on High performance embedded architectures and compilers
Offset assignment showdown: evaluation of DSP address code optimization algorithms
CC'03 Proceedings of the 12th international conference on Compiler construction
Evaluating address register assignment and offset assignment algorithms
ACM Transactions on Embedded Computing Systems (TECS)
Storage Optimization through Offset Assignment with Variable Coalescing
ACM Transactions on Embedded Computing Systems (TECS)
An ILP solution to address code generation for embedded applications on digital signal processors
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
Minimizing address arithmetic instructions in embedded applications on DSPs
Computers and Electrical Engineering
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This paper presents a new approach to solving the DSP address assignment problem. A minimum cost circulation approach is used to efficiently generate high performance addressing code in polynomial time. Addressing code size improvements of up to 7 times are obtained, accounting for up to 1.6 times improvement in code size and performance of compiler-generated DSP code. Results also show that memory layout has a small effect on code size and performance when optimal addressing is used. This research is important for industry since this value-added technique can improve code size, power dissipation and performance, without increasing cost.