An empirical comparison of algorithmic, instruction, and architectural power prediction models for high performance embedded DSP processors

Authors:
Catherine H. Gebotys;Robert J. Gebotys
Affiliations:
Department of Electrical and Computer Engineering, University of Waterloo, Wilfrid Laurier University, Waterloo, Ont, Canada;-
Venue:
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Year:
1998

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Abstract

This paper presents a comparison of statistically-derived power prediction models at the algorithmic, instruction, and architectural levels for embedded high performance DSP processors. The approach is general enough to be applied to any embedded DSP processor. Results from 168 power measurements of DSP code show that power can be predicted at instruction and architecture levels with less than 2% error. This result is important for developing a general methodology for power characterization of embedded DSP software since low power is critical to complex DSP applications in many cost sensitive markets.