ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Synthesis of application specific instructions for embedded DSP software
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Low-Power Design for Real-Time Systems
Real-Time Systems
Synthesis of Application Specific Instructions for Embedded DSP Software
IEEE Transactions on Computers
Power optimization using divide-and-conquer techniques for minimization of the number of operations
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Instruction-level power estimation for embedded VLIW cores
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
System-level power optimization: techniques and tools
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power minimization derived from architectural-usage of VLIW processors
Proceedings of the 37th Annual Design Automation Conference
Function-level power estimation methodology for microprocessors
Proceedings of the 37th Annual Design Automation Conference
Low power synthesis of sum-of-products computation (poster session)
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Profile-driven code execution for low power dissipation (poster session)
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Instruction scheduling for power reduction in processor-based system design
Proceedings of the conference on Design, automation and test in Europe
Computer Aided Design of Fault-Tolerant Application Specific Programmable Processors
IEEE Transactions on Computers
Retargetable compilation for low power
Proceedings of the ninth international symposium on Hardware/software codesign
Run-time power estimation in high performance microprocessors
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Software implementation strategies for power-conscious systems
Mobile Networks and Applications
An Accurate Instruction-Level Energy Consumption Model for Embedded RISC Processors
OM '01 Proceedings of the 2001 ACM SIGPLAN workshop on Optimization of middleware and distributed systems
Compiler optimization on instruction scheduling for low power
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Code generation for embedded processors
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Heterogeneous memory management for embedded systems
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
Energy estimation and optimization of embedded VLIW processors based on instruction clustering
Proceedings of the 39th annual Design Automation Conference
Towards energy-aware software-based fault tolerance in real-time systems
Proceedings of the 2002 international symposium on Low power electronics and design
On achieving balanced power consumption in software pipelined loops
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
An optimal memory allocation scheme for scratch-pad-based embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Power exploration for embedded VLIW architectures
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Application-driven processor design exploration for power-performance trade-off analysis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Energy Metric for Software Systems
Software Quality Control
Compiler Design Issues for Embedded Processors
IEEE Design & Test
Instruction-level power consumption estimation of embedded processors for low-power applications
Computer Standards & Interfaces - Intelligent data acquisition and advanced computing systems
ISHPC '02 Proceedings of the 4th International Symposium on High Performance Computing
Instrumentation Set-up for Instruction Level Power Modeling
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Compiler optimization on VLIW instruction scheduling for low power
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Compiler optimizations for low power systems
Power aware computing
RTAS '03 Proceedings of the The 9th IEEE Real-Time and Embedded Technology and Applications Symposium
Power efficient data path synthesis of sum-of-products computations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Compiler-decided dynamic memory allocation for scratch-pad based embedded systems
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Managing battery lifetime with energy-aware adaptation
ACM Transactions on Computer Systems (TOCS)
Managing battery lifetime with energy-aware adaptation
ACM Transactions on Computer Systems (TOCS)
Dynamic Functional Unit Assignment for Low Power
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Energy macromodeling of embedded operating systems
ACM Transactions on Embedded Computing Systems (TECS)
Journal of VLSI Signal Processing Systems
Power-Performance Simulation and Design Strategies for Single-Chip Heterogeneous Multiprocessors
IEEE Transactions on Computers
Dynamic functional unit assignment for low power
The Journal of Supercomputing
Instantaneous current modeling in a complex VLIW processor core
ACM Transactions on Embedded Computing Systems (TECS)
A sink-n-hoist framework for leakage power reduction
Proceedings of the 5th ACM international conference on Embedded software
HyPE: hybrid power estimation for IP-based programmable systems
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Instruction scheduling of VLIW architectures for balanced power consumption
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Compilers for leakage power reduction
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Loop scheduling with timing and switching-activity minimization for VLIW DSP
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Dynamic current modeling at the instruction level
Proceedings of the 2006 international symposium on Low power electronics and design
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Instruction level energy modeling for pipelined processors
Journal of Embedded Computing - Low-power Embedded Systems
Compilation for compact power-gating controls
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Recursive function data allocation to scratch-pad memory
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
Energy-optimizing source code transformations for operating system-driven embedded software
ACM Transactions on Embedded Computing Systems (TECS)
Algorithms and analysis of scheduling for loops with minimum switching
International Journal of Computational Science and Engineering
ACM SIGARCH Computer Architecture News - Special issue: ALPS '07---advanced low power systems
High-level safety mechanisms for safety-critical application-specific low power devices
ICCOMP'05 Proceedings of the 9th WSEAS International Conference on Computers
Energy-Aware Loop Scheduling and Assignment for Multi-Core, Multi-Functional-Unit Architecture
Journal of Signal Processing Systems
Developing an environment for embedded software energy estimation
Computer Standards & Interfaces
Journal of Embedded Computing - PATMOS 2007 selected papers on low power electronics
A genetic algorithm for energy efficient device scheduling in real-time systems
GECCO'03 Proceedings of the 2003 international conference on Genetic and evolutionary computation: PartII
ECOOP'07 Proceedings of the 2007 conference on Object-oriented technology
Implementation, compilation, optimization of object-oriented languages, programs and systems
ECOOP'06 Proceedings of the 2006 conference on Object-oriented technology: ECOOP 2006 workshop reader
A High-level Microprocessor Power Modeling Technique Based on Event Signatures
Journal of Signal Processing Systems
Generating power-hungry test programs for power-aware validation of pipelined processors
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
Power aware SID-based simulator for embedded multicore DSP subsystems
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
SOFSEM'11 Proceedings of the 37th international conference on Current trends in theory and practice of computer science
Energy consumption and execution time estimation of embedded system applications
Microprocessors & Microsystems
A multi-granularity power modeling methodology for embedded processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Compiler analysis and supports for leakage power reduction on microprocessors
LCPC'02 Proceedings of the 15th international conference on Languages and Compilers for Parallel Computing
Fast and accurate embedded systems energy characterization using non-intrusive measurements
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Power devil: tool for power gating strategy selection
Proceedings of the 10th Workshop on Optimizations for DSP and Embedded Systems
Post-compiler software optimization for reducing energy
Proceedings of the 19th international conference on Architectural support for programming languages and operating systems
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Power is becoming a critical constraint for designing embedded applications. Current power analysis techniques based on circuit-level or architectural-level simulation are either impractical or inaccurate to estimate the power cost for a given piece of application software. In this paper, an instruction-level power analysis model is developed for an embedded digital signal processor (DSP) based on physical current measurements. Significant points of difference have been observed between the software power model for this custom DSP processor and the power models that have been developed earlier for some general purpose commercial microprocessors. In particular, the effect of circuit state on the power cost of an instruction stream is more marked in the case of this DSP processor. In addition, the processor has special architectural features that allow dual memory accesses and packing of instructions into pairs. The energy reduction possible through the use of these features is studied. The on-chip Booth multiplier on the processor is a major source of energy consumption for DSP programs. A microarchitectural power model for the multiplier is developed and analyzed for further power minimization. In order to exploit all of the above effects, a scheduling technique based on the new instruction-level power model is proposed. Several example programs are provided to illustrate the effectiveness of this approach. Energy reductions varying from 26% to 73% have been observed. These energy savings are real and have been verified through physical measurement. It should be noted that the energy reduction essentially comes for free. It is obtained through software modification, and thus, entails no hardware overhead. In addition, there is no loss of performance since the running times of the modified programs either improve or remain unchanged.