Power analysis of embedded software: a first step towards software power minimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Power analysis and minimization techniques for embedded DSP software
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The filter cache: an energy efficient memory structure
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Reducing power in high-performance microprocessors
DAC '98 Proceedings of the 35th annual Design Automation Conference
Pipeline gating: speculation control for energy reduction
Proceedings of the 25th annual international symposium on Computer architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Code compression for low power embedded system design
Proceedings of the 37th Annual Design Automation Conference
Thermal Management System for High Performance PowerPCTM Microprocessors
COMPCON '97 Proceedings of the 42nd IEEE International Computer Conference
Power aware microarchitecture resource scaling
Proceedings of the conference on Design, automation and test in Europe
New directions in compiler technology for embedded systems (embedded tutorial)
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Microarchitecture-level power management
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Input Space Adaptive Embedded Software Synthesis
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Energy efficient co-adaptive instruction fetch and issue
Proceedings of the 30th annual international symposium on Computer architecture
Routine based OS-aware microprocessor resource adaptation for run-time operating system power saving
Proceedings of the 2003 international symposium on Low power electronics and design
Optimizing Array-Intensive Applications for On-Chip Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
Dynamic voltage and frequency scaling for scientific applications
LCPC'01 Proceedings of the 14th international conference on Languages and compilers for parallel computing
The challenges of massive on-chip concurrency
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Survey of Low-Energy Techniques for Instruction Memory Organisations in Embedded Systems
Journal of Signal Processing Systems
Hi-index | 0.00 |
This paper proposes a novel technique for power-performance trade-off based on profile-driven code execution. Specifically, we show that there is an optimal level of parallelism for energy consumption and propose a compiler-assisted technique for code annotation that can be used at run-time to adaptively trade-off power and performance. As shown by experimental results, our approach is up to 23% better than clock throttling and is as efficient as voltage scaling (up to 10% better in some cases). The technique proposed in this paper can be used by an ACPI-compliant power manager for prolonging battery life or as a passive cooling feature for thermal management.