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ICS '98 Proceedings of the 12th international conference on Supercomputing
Advanced compiler design and implementation
Advanced compiler design and implementation
New tiling techniques to improve cache temporal locality
Proceedings of the ACM SIGPLAN 1999 conference on Programming language design and implementation
Influence of compiler optimizations on system power
Proceedings of the 37th Annual Design Automation Conference
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Design issues for dynamic voltage scaling
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Profile-driven code execution for low power dissipation (poster session)
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Dynamic voltage scaling on a low-power microprocessor
Proceedings of the 7th annual international conference on Mobile computing and networking
Compiler-directed dynamic voltage/frequency scheduling for energy reduction in microprocessors
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Measuring Experimental Error in Microprocessor Simulation
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Intra-Task Voltage Scheduling for Low-Energy, Hard Real-Time Applications
IEEE Design & Test
Improving Effective Bandwidth through Compiler Enhancement of Global Cache Reuse
IPDPS '01 Proceedings of the 15th International Parallel & Distributed Processing Symposium
Reducing DRAM Latencies with an Integrated Memory Hierarchy Design
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Policies for dynamic clock scheduling
OSDI'00 Proceedings of the 4th conference on Symposium on Operating System Design & Implementation - Volume 4
The design, implementation, and evaluation of a compiler algorithm for CPU energy reduction
PLDI '03 Proceedings of the ACM SIGPLAN 2003 conference on Programming language design and implementation
Exploiting Processor Workload Heterogeneity for Reducing Energy Consumption in Chip Multiprocessors
Proceedings of the conference on Design, automation and test in Europe - Volume 2
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Dynamic voltage and frequency scaling (DVFS) of the CPU has been shown to be one of the most effective ways to reduce energy consumption of a program. This paper discusses the benefit of dynamic voltage and frequency scaling for scientific applications under different optimization levels. The reported experiments show that there are still many opportunities to apply DVFS to the highly optimized codes, and the profitability is significant across the benchmarks. It is also observed that there are performance and energy consumption tradeoffs for different optimization levels in the presence of DVFS. While in general compiling for performance will improve energy usage as well, in some cases the less successful optimization lead to higher energy savings. Finally, a comparison of the benefits of operating system support versus compiler support for DVFS is discussed.