Profile guided code positioning
PLDI '90 Proceedings of the ACM SIGPLAN 1990 conference on Programming language design and implementation
A survey of power management techniques in mobile computing operating systems
ACM SIGOPS Operating Systems Review
Power Optimization in VLSI Layout: A Survey
Journal of VLSI Signal Processing Systems
Survey of low power techniques for ROMs
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
The filter cache: an energy efficient memory structure
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Instruction buffering to reduce power in processors for signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
A power reduction technique with object code merging for application specific embedded processors
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Profile-driven code execution for low power dissipation (poster session)
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Data and memory optimization techniques for embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Research challenges in wireless networks of biomedical sensors
Proceedings of the 7th annual international conference on Mobile computing and networking
A history-based I-cache for low-energy multimedia applications
Proceedings of the 2002 international symposium on Low power electronics and design
ACM Transactions on Embedded Computing Systems (TECS)
Computer
Power Efficient Topologies for Wireless Sensor Networks
ICPP '02 Proceedings of the 2001 International Conference on Parallel Processing
Energy and Performance Improvements in Microprocessor Design Using a Loop Cache
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
A Code Transformation-Based Methodology for Improving I-Cache Performance of DSP Applications
Proceedings of the conference on Design, automation and test in Europe
Power Savings in Embedded Processors through Decode Filer Cache
Proceedings of the conference on Design, automation and test in Europe
Dynamic Filter Cache for Low Power Instruction Memory Hierarchy
DSD '04 Proceedings of the Digital System Design, EUROMICRO Systems
Optimizing the Memory Bandwidth with Loop Morphing
ASAP '04 Proceedings of the Application-Specific Systems, Architectures and Processors, 15th IEEE International Conference
A Distributed Control Path Architecture for VLIW Processors
Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques
Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Computer Architecture, Fourth Edition: A Quantitative Approach
Computer Architecture, Fourth Edition: A Quantitative Approach
Real-time Performance Analysis for Wireless Sensor Networks
NPC '07 Proceedings of the 2007 IFIP International Conference on Network and Parallel Computing Workshops
Extending Multicore Architectures to Exploit Hybrid Parallelism in Single-thread Applications
HPCA '07 Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture
Hierarchical Instruction Register Organization
IEEE Computer Architecture Letters
Advanced Memory Optimization Techniques for Low-Power Embedded Processors
Advanced Memory Optimization Techniques for Low-Power Embedded Processors
Ultra-Low Energy Domain-Specific Instruction-Set Processors
Ultra-Low Energy Domain-Specific Instruction-Set Processors
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Instruction memory organisations have been pointed out as one of the major sources of energy consumption in embedded systems. As embedded systems are characterised by restrictive resources and a low-energy budget, any enhancement that is introduced into this component of the system will allow embedded designers not only to decrease the total energy consumption, but also to have a better distribution of the energy budget throughout the whole system. The work that is presented in this paper provides a synthesis on the low-energy techniques that are used in instruction memory organisations, outlining their comparative advantages, drawbacks, and trade-offs. Apart from giving the reader a first grasp on the fundamental characteristics and design constraints of various types of instruction memory organisations, the architectural classification that is presented in this paper has the advantage of clearly exhibiting lesser explored techniques, and hence providing hints for future research on instructions memory organisations that are used in embedded systems.