On the energy-efficiency of software transactional memory
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Design and Tool Flow of Multimedia MPSoC Platforms
Journal of Signal Processing Systems
Acceleration of the L4/Fiasco microkernel using scratchpad memory
Proceedings of the First Workshop on Virtualization in Mobile Computing
Optimal static WCET-aware scratchpad allocation of program code
Proceedings of the 46th Annual Design Automation Conference
Versatile system-level memory-aware platform description approach for embedded MPSoCs
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems
Experience with Widening Based Equivalence Checking in Realistic Multimedia Systems
Journal of Electronic Testing: Theory and Applications
A compiler framework for the reduction of worst-case execution times
Real-Time Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architecture extensions for efficient management of scratch-pad memory
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Equivalence checking of static affine programs using widening to handle recurrences
ACM Transactions on Programming Languages and Systems (TOPLAS)
Survey of Low-Energy Techniques for Instruction Memory Organisations in Embedded Systems
Journal of Signal Processing Systems
Journal of Signal Processing Systems
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The design of embedded systems warrants a new perspective because of the following two reasons: Firstly, slow and energy inefficient memory hierarchies have already become the bottleneck of the embedded systems. It is documented in the literature as the memory wall problem. Secondly, the software running on the contemporary embedded devices is becoming increasingly complex. It is also well understood that no silver bullet exists to solve the memory wall problem. Therefore, this book explores a collaborative approach by proposing novel memory hierarchies and software optimization techniques for the optimal utilization of these memory hierarchies. Linking memory architecture design with memory-architecture aware compilation results in fast, energy-efficient and timing predictable memory accesses. The evaluation of the optimization techniques using real-life benchmarks for a single processor system, a multiprocessor system-on-chip (SoC) and for a digital signal processor system, reports significant reductions in the energy consumption and performance improvement of these systems. The book presents a wide range of optimizations, progressively increasing in the complexity of analysis and of memory hierarchies. The final chapter covers optimization techniques for applications consisting of multiple processes found in most modern embedded devices. Advanced Memory Optimization Techniques for Low Power Embedded Processorsis designed for researchers, complier writers and embedded system designers / architects who wish to optimize the energy and performance characteristics of the memory subsystem.